Is FCVT.LU.D available on RV32?
No. The official F/D conversion rules define the L/LU 64-bit integer forms as RV64-only.
FCVT.LU.D
RISC-V FCVT.LU.D Instruction Details
Instruction ManualOP-FP conversion fieldsRV64 double precision-to-unsigned 64-bit integer conversion, rounded by rm/frm and written to integer rd.
Instruction Syntax
fcvt.lu.d rd, rs1, rm
Operand Breakdown
This is a OP-FP conversion fields-format instruction. Confirm operand positions based on the assembly syntax.
DFloating-Point Convert
Instruction Behavior
FCVT.LU.D is an RV64-only floating-point-to-integer conversion. It rounds the double precision value in f[rs1] according to rm to an unsigned 64-bit integer and writes x[rd]; NX is set only when the rounded result differs from the source and NV is not set. On invalid conversion, negative out-of-range input or -infinity yields 0, while positive out-of-range input, +infinity, or NaN yields 2^64-1, and NV is set.
FCVT.LU.D Decode And Execute Animation
Shows the D-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.lu.d
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=D (01)
rs2=LU
rounding: RNE nearest-even
fflags: NX
RV64-only
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.LU
01
fmt=D
00011
rs2=LU
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC2358553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 01 -> FCVT.LU.D
rs2
00011 -> LU target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = 42.75
convert
42.75 -> uint64 43
write
a0(x10) = 43; NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xC2358553
syntax : fcvt.lu.d a0(x10), fa1(f11), rne
result : a0(x10) = 43; NX
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
D FP source
42.75
conversion
42.75 -> uint64 43
writeback
a0(x10) = 43
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only D-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
RV64 double precision-to-unsigned 64-bit integer conversion, rounded by rm/frm and written to integer rd.
OP-FP opcode is 1010011; funct5=11000 denotes FP-to-integer FCVT.
fmt=01 denotes the double precision source format; rs2=00011 selects LU as the integer target, not a normal second source register.
rd is an integer register and rs1 is an FP register; NaN, infinity, or out-of-range inputs set NV by the official invalid-conversion rule.
This L/LU form is RV64-only; RV32 pages should not present it as an available instruction.
Common Usage Scenarios
RV64 floating-point and 64-bit integer conversion
Understand this scenario with real code like «fcvt.lu.d x10, f0, rtz # f0 = 42.75 -> x10 = 42; NX (RV64)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OP-FP conversion fields.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
L/LU forms are RV64-only; do not use them on RV32.
rd is an integer register and rs1 is an FP register; the rs2 field only selects the L/LU format.
NaN, infinity, or out-of-range input does not wrap like integer overflow; it sets NV by the official invalid-conversion rule.
NX is set only when rounding changes the source and NV is not set; a negative fraction rounded to 0 is valid.
FAQ
Which register classes do rd and rs1 use in FCVT.LU.D?
This is an FP-to-integer conversion: rd is an integer register and rs1 is an FP register.
What does the rs2 field mean in FCVT.LU.D?
The rs2 field selects the LU unsigned 64-bit integer format; it is not a second source operand in assembly syntax.