Is FCVT.L.D available on RV32?
No. The official F/D conversion rules define the L/LU 64-bit integer forms as RV64-only.
FCVT.L.D
RISC-V FCVT.L.D Instruction Details
Instruction ManualR-typeRV64 double precision-to-signed 64-bit integer conversion, rounded by rm/frm and written to integer rd.
Instruction Syntax
fcvt.l.d rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
DFloating-Point Convert
Instruction Behavior
FCVT.L.D is an RV64-only floating-point-to-integer conversion. It rounds the double precision value in f[rs1] according to rm to a signed 64-bit integer and writes x[rd]; inexact conversion sets NX, while NaN, infinity, or out-of-range input sets NV by the official invalid-conversion rule.
FCVT.L.D Decode And Execute Animation
Shows the D-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, rm rounding, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.l.d
,
,
Execution Context
fmt=L (00)
rs2=L
rounding: RNE nearest-even
fflags: NX
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.L
00
fmt=L
00010
rs2=L
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC0258553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 00 -> FCVT.L.D
rs2
00010 -> L target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = -42.75
convert
-42.75 -> int64 -43
write
a0(x10) = -43; NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT conversion instructions use opcode 1010011.
encoding: 0xC0258553
syntax : fcvt.l.d a0(x10), fa1(f11), rne
result : a0(x10) = -43; NX
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
D FP source
-42.75
conversion
-42.75 -> int64 -43
writeback
a0(x10) = -43
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only D-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.l.d is an RV64-only FCVT.L.D form: it reads a double precision FP register, rounds according to rm/frm to a signed 64-bit integer, and writes integer rd.
OP-FP opcode is 1010011; funct5=11000 denotes FP-to-integer FCVT.
fmt=01 denotes the double precision source format; rs2=00010 selects L as the integer target, not a normal second source register.
rd is an integer register and rs1 is an FP register; NaN, infinity, or out-of-range inputs set NV by the official invalid-conversion rule.
This L/LU form is RV64-only; RV32 pages should not present it as an available instruction.
Common Usage Scenarios
Type Conversion
Understand this scenario with real code like «fcvt.l.d x10, f0, rtz # x10 = (long)f0 (RV64)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
L/LU forms are RV64-only; do not use them on RV32.
rd is an integer register and rs1 is an FP register; the rs2 field only selects the L/LU format.
NaN, infinity, or out-of-range input does not wrap like integer overflow; it sets NV by the official invalid-conversion rule.
NX is set when a fractional FP source is rounded to a different integer value.
FAQ
Which register classes do rd and rs1 use in FCVT.L.D?
This is an FP-to-integer conversion: rd is an integer register and rs1 is an FP register.
What does the rs2 field mean in FCVT.L.D?
The rs2 field selects the L signed 64-bit integer format; it is not a second source operand in assembly syntax.