Is FCVT.L.D available on RV32?
No. The official F/D conversion rules define the L/LU 64-bit integer forms as RV64-only.
FCVT.L.D
RISC-V FCVT.L.D Instruction Details
Instruction ManualOP-FPRV64 double precision-to-signed 64-bit integer conversion, rounded by rm/frm and written to integer rd.
Instruction Syntax
fcvt.l.d rd, rs1[, rm]
Syntax: fcvt.l.d rd, rs1[, rm]; integer rd, FP rs1; omitted rm defaults to dyn using frm.
32-bit OP-FP: funct7=1100001, rs2=00010, funct3=rm, opcode=1010011. rs2 is a fixed selector, not a second source operand.
RV64-only D 2.2 (requires F); enable required extensions and FP state. Round to int64 using rm. Negative overflow/-infinity gives -2^63; positive overflow/+infinity/NaN gives 2^63−1 and sets NV. NX requires a changed result with NV clear.
With FLEN>64, invalid source NaN-boxing becomes canonical NaN. rd=x0 discards the result but retains flag effects. Static rm=101/110 and dynamic frm=101–111 have reserved behavior; the animation fixes DYN frm=RNE. Initial fflags=0 is an animation assumption; instructions do not clear accrued flags.
DFloating-Point Convert
Instruction Behavior
FCVT.L.D is RV64-only. It rounds f[rs1] according to rm to signed 64-bit x[rd]. An unrepresentable rounded result sets NV: negative out-of-range or -infinity gives -2^63; positive out-of-range, +infinity, or NaN gives 2^63-1. NX is set only when the result differs and NV is clear.
FCVT.L.D Decode And Execute Animation
Shows the D-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.l.d
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=D (01)
rs2=L
rounding: RNE nearest-even
fflags: NX
RV64-only
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.L
01
fmt=D
00010
rs2=L
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC2258553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 01 -> FCVT.L.D
rs2
00010 -> L target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = -42.75
convert
-42.75 -> int64 -43
write
a0(x10) = -43; NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xC2258553
syntax : fcvt.l.d a0(x10), fa1(f11), rne
result : a0(x10) = -43; NX
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
D FP source
-42.75
conversion
-42.75 -> int64 -43
writeback
a0(x10) = -43
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only D-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.l.d is an RV64-only FCVT.L.D form: it reads a double precision FP register, rounds according to rm/frm to a signed 64-bit integer, and writes integer rd.
OP-FP opcode is 1010011; funct5=11000 denotes FP-to-integer FCVT.
fmt=01 denotes the double precision source format; rs2=00010 selects L as the integer target, not a normal second source register.
rd is an integer register and rs1 is an FP register; NaN, infinity, or out-of-range inputs set NV by the official invalid-conversion rule.
RV64 only; enable the required extensions and FP state. Optional rm defaults to dyn using frm; rm=101/110 or dynamic frm=101–111 has reserved behavior.
Common Usage Scenarios
64-bit Numeric Conversion
fcvt.l.d x10, f0, rtz # RV64; f0=1.5 -> x10=1, NX (initial fflags=0). Enable the listed extensions and FP state and initialize the stated source; the result follows the classification or rounding rules on this page.
Pre-Use Checklist
Syntax Check
- Syntax: fcvt.l.d rd, rs1[, rm]; integer rd, FP rs1; omitted rm defaults to dyn using frm.
- 32-bit OP-FP: funct7=1100001, rs2=00010, funct3=rm, opcode=1010011. rs2 is a fixed selector, not a second source operand.
Semantic Check
- RV64-only D 2.2 (requires F); enable required extensions and FP state. Round to int64 using rm. Negative overflow/-infinity gives -2^63; positive overflow/+infinity/NaN gives 2^63−1 and sets NV. NX requires a changed result with NV clear.
- With FLEN>64, invalid source NaN-boxing becomes canonical NaN. rd=x0 discards the result but retains flag effects. Static rm=101/110 and dynamic frm=101–111 have reserved behavior; the animation fixes DYN frm=RNE. Initial fflags=0 is an animation assumption; instructions do not clear accrued flags.
Pitfalls / Common Confusions
L/LU forms are RV64-only; do not use them on RV32.
rd is an integer register and rs1 is an FP register; the rs2 field only selects the L/LU format.
NaN, infinity, or out-of-range input does not wrap like integer overflow; it sets NV by the official invalid-conversion rule.
NX is set only if the rounded result differs and NV is clear; accrued fflags are not cleared.
FAQ
Which register classes do rd and rs1 use in FCVT.L.D?
This is an FP-to-integer conversion: rd is an integer register and rs1 is an FP register.
What does the rs2 field mean in FCVT.L.D?
The rs2 field selects the L signed 64-bit integer format; it is not a second source operand in assembly syntax.