Is rs2 a source register in fcvt.h.d?
No. The assembly syntax has rd, rs1, rm only; the encoded rs2 field selects the source D FP format.
FCVT.H.D
RISC-V FCVT.H.D Instruction Details
Instruction ManualR-typeConvert double-precision FP to half-precision FP; narrowing conversion rounds according to rm.
Instruction Syntax
fcvt.h.d rd, rs1, rm
rd selects f0–f31; rs1 selects FP f0–f31; rs2 selects format D, not a second source register.
32-bit OP-FP: funct5=01000, fmt=10, rs2=00001, opcode=1010011; no immediate.
Requires Zfhmin+D on RV32/RV64; rm/frm controls narrowing to H. Optional rm defaults to dyn; reserved rounding encodings remain reserved.
Enable required extensions and FP state. Check FP-source NaN-boxing when narrower than FLEN; a narrower destination gets upper ones. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.
ZfhminDFloating-Point Convert
Instruction Behavior
fcvt.h.d reads a double-precision source value from FP register rs1, converts it to a half-precision FP result, and writes FP register rd. In the OP-FP encoding, fmt=H (10) denotes the destination format and rs2=D (01) denotes the source format; this narrowing conversion rounds according to rm/frm when the destination format cannot represent the source exactly and may set FP exception flags.
FCVT.H.D Decode And Execute Animation
Shows the Zfhmin + D-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the floating-point destination.
rd
rs1
rm
fcvt.h.d
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=H (10)
rs2=D
rounding: RNE nearest-even
fflags: 0
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FCVT.H
10
fmt=H
00001
rs2=D
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x44158553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + 10 -> FCVT.H.D
rs2
00001 -> D source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / fa1(f11)
read
fa1(f11) = D 1.25 (0x3FF4000000000000)
convert
D 1.25 -> H 1.25
write
fa0(f10) = H 1.25 (0x3D00); 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0x44158553
syntax : fcvt.h.d fa0(f10), fa1(f11), rne
result : fa0(f10) = H 1.25 (0x3D00); 0
D-to-H is a floating-point narrowing conversion; the current example is exactly representable by the target format and leaves fflags at 0.
FCVT Conversion View
D FP source
D 1.25 (0x3FF4000000000000)
conversion
D 1.25 -> H 1.25
writeback
fa0(f10) = H 1.25 (0x3D00)
D-to-H is a floating-point narrowing conversion; the current example is exactly representable by the target format and leaves fflags at 0.
This animation shows only Zfhmin + D-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.h.d is an FP-to-FP format conversion: rd and rs1 are FP registers, fmt encodes destination H, and rs2 encodes source D. The narrowing conversion rounds according to rm/frm and may set FP exception flags such as NX, OF, or UF.
OP-FP opcode is 1010011; funct5=01000 denotes FP-to-FP format FCVT.
fmt=10 selects destination H (half-precision); rs2=00001 selects source D (double-precision).
rd and rs1 are both FP registers; the rs2 field is a source-format selector, not an assembly operand.
Zfhmin combined with D supports this H/D conversion.
The narrowing conversion rounds according to rm or dynamic frm when needed and records applicable FP exception flags in fflags.
NaN-boxing applies to source checking and destination writeback in wider FLEN registers; the animation does not enumerate every NaN payload or special-value combination.
An optional lowercase rm operand defaults to dyn (rm=111), which uses current frm; reserved rounding encodings have reserved behavior.
Examples assume required extensions and FP state are enabled and initial fflags=0. Exception flags accrue; setting a flag does not itself cause an FP exception trap.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — D Extension, Version 2.2The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Zfh and Zfhmin, Version 1.0The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F Extension, Version 2.2RISC-V Assembly Programmer's Manual — v0.0.1, Floating-point rounding modes
Common Usage Scenarios
Floating-Point Format Conversion
Understand this scenario with real code like «fcvt.h.d f0, f1, rne # 1.25 -> 1.25; initial f1=1.25 (valid D), fflags=0».
Type Conversion
Understand this scenario with real code like «fcvt.h.d f0, f1, rne # 1.25 -> 1.25; initial f1=1.25 (valid D), fflags=0».
Pre-Use Checklist
Syntax Check
- rd selects f0–f31; rs1 selects FP f0–f31; rs2 selects format D, not a second source register.
- 32-bit OP-FP: funct5=01000, fmt=10, rs2=00001, opcode=1010011; no immediate.
Semantic Check
- Requires Zfhmin+D on RV32/RV64; rm/frm controls narrowing to H. Optional rm defaults to dyn; reserved rounding encodings remain reserved.
- Enable required extensions and FP state. Check FP-source NaN-boxing when narrower than FLEN; a narrower destination gets upper ones. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.
Pitfalls / Common Confusions
fmt=H selects the destination half-precision format; rs2=D selects the source double-precision format and is not a second source register.
Zfhmin combined with D supports this H/D conversion.
This is a floating-point narrowing conversion; rm or dynamic frm selects rounding when the destination format cannot represent the source exactly.
The FP source in a wider FLEN register must satisfy NaN-boxing; the result is NaN-boxed according to the destination format.
The animation accepts the listed finite D-format examples, including 1.1 for observing rounding; other values, NaNs, infinities, overflow, underflow, and payload paths are outside its scope.
FAQ
When does fcvt.h.d use rm?
When the destination format cannot exactly represent the source value, rm or dynamic frm selects the rounding direction.
How is fcvt.h.d different from integer FCVT forms?
In this form, both rd and rs1 are FP registers; W/WU/L/LU forms convert between integer and FP registers.