Is rs2 a register operand?
No; rs2 encodes the S source format. Assembly operands are rd, rs1, rm.
FCVT.H.S
RISC-V FCVT.H.S Instruction Details
Instruction ManualR-typeConvert single-precision FP to half-precision FP; narrowing conversion rounds according to rm.
Instruction Syntax
fcvt.h.s rd, rs1, rm
rd selects FP f0–f31, including writable f0; rs1 selects FP f0–f31; rs2 is a format selector, not a second source register.
32-bit OP-FP: funct5=01000, fmt=10, rs2=00000, opcode=1010011; no immediate.
RV32/RV64 Zfhmin (also included in Zfh); enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
FP sources narrower than FLEN require NaN-boxing checks; an invalid box is treated as a canonical source-format NaN. An H result gets upper ones when FLEN>16. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP trap.
ZfhminFloating-Point Convert
Instruction Behavior
fcvt.h.s reads a single-precision source value from FP register rs1, converts it to a half-precision FP result, and writes FP register rd. In the OP-FP encoding, fmt=H (10) denotes the destination format and rs2=S (00) denotes the source format; this narrowing conversion rounds according to rm/frm when the destination format cannot represent the source exactly and may set FP exception flags.
FCVT.H.S Decode And Execute Animation
Shows the Zfhmin-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the floating-point destination.
rd
rs1
rm
fcvt.h.s
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=H (10)
rs2=S
rounding: RNE nearest-even
fflags: 0
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FCVT.H
10
fmt=H
00000
rs2=S
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x44058553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + 10 -> FCVT.H.S
rs2
00000 -> S source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / fa1(f11)
read
fa1(f11) = S 1.25 (0x3FA00000)
convert
S 1.25 -> H 1.25
write
fa0(f10) = H 1.25 (0x3D00); 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0x44058553
syntax : fcvt.h.s f10, f11, rne
result : fa0(f10) = H 1.25 (0x3D00); 0
S-to-H is a floating-point narrowing conversion; the current example is exactly representable by the target format and leaves fflags at 0.
FCVT Conversion View
S FP source
S 1.25 (0x3FA00000)
conversion
S 1.25 -> H 1.25
writeback
fa0(f10) = H 1.25 (0x3D00)
S-to-H is a floating-point narrowing conversion; the current example is exactly representable by the target format and leaves fflags at 0.
This animation shows only Zfhmin-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.h.s is an FP-to-FP format conversion: rd and rs1 are FP registers, fmt encodes destination H, and rs2 encodes source S. The narrowing conversion rounds according to rm/frm and may set FP exception flags such as NX, OF, or UF.
OP-FP opcode is 1010011; funct5=01000 denotes FP-to-FP format FCVT.
fmt=10 selects destination H (half-precision); rs2=00000 selects source S (single-precision).
rd and rs1 are both FP registers; the rs2 field is a source-format selector, not an assembly operand.
The narrowing conversion rounds according to rm or dynamic frm when needed and records applicable FP exception flags in fflags.
Omitting rm defaults to dyn (111), selecting frm; static 101/110 and dynamic frm=101–111 are reserved. fflags accrues exceptions; setting a flag does not itself generate an FP trap.
The H result occupies the low 16 bits, with all upper bits set to 1 when FLEN>16. A source narrower than FLEN that is not properly NaN-boxed is treated as a canonical NaN of its source format.
Common Usage Scenarios
Floating-Point Format Conversion
Understand this scenario with real code like «fcvt.h.s f0, f1, rne # H result 1.25; no new fflags; f1: S value 1.25; required extensions/FP state enabled».
Type Conversion
Understand this scenario with real code like «fcvt.h.s f0, f1, rne # H result 1.25; no new fflags; f1: S value 1.25; required extensions/FP state enabled».
Pre-Use Checklist
Syntax Check
- rd selects FP f0–f31, including writable f0; rs1 selects FP f0–f31; rs2 is a format selector, not a second source register.
- 32-bit OP-FP: funct5=01000, fmt=10, rs2=00000, opcode=1010011; no immediate.
Semantic Check
- RV32/RV64 Zfhmin (also included in Zfh); enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
- FP sources narrower than FLEN require NaN-boxing checks; an invalid box is treated as a canonical source-format NaN. An H result gets upper ones when FLEN>16. Applicable exceptions accrue in fflags; setting a flag does not itself cause an FP trap.
Pitfalls / Common Confusions
fmt=H selects the destination half-precision format; rs2=S selects the source single-precision format and is not a second source register.
This is a floating-point narrowing conversion; rm or dynamic frm selects rounding when the destination format cannot represent the source exactly.
The H result occupies the low 16 bits, with all upper bits set to 1 when FLEN>16. A source narrower than FLEN that is not properly NaN-boxed is treated as a canonical NaN of its source format.
FAQ
When does rm matter?
For inexact conversions, rm or dynamic frm selects the rounding direction.
How does this differ from integer FCVT?
Both operands are FP registers; W/WU/L/LU convert between integer and FP registers.
What happens to NaNs and infinities?
Infinity retains its sign. A NaN result is the target canonical NaN; sNaN sets NV. Finite narrowing may raise NX, OF, or UF; the animation covers only the listed finite exact examples.