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FCVT.S.H

RISC-V FCVT.S.H Instruction Details

Instruction ManualR-type

Convert half-precision float to single-precision float

Instruction Syntax

fcvt.s.h rd, rs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZfhZfhminFloating-Point Convert
Related Search Terms
fcvt.s.h instructionhalf-precision to single-precisionfcvt.s.h conversionfcvt.s.h exact conversionfcvt.s.h floating point

Instruction Behavior

fcvt.s.h converts a half-precision source operand to a wider single-precision result. This floating-point widening conversion is exact and does not round.

Quick Understanding & Search Notes

fcvt.s.h converts a half-precision source operand to a wider single-precision result. This floating-point widening conversion is exact and does not round.

The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.
This is a floating-point widening conversion, not a narrowing conversion; rm does not affect the numeric result.
The floating-point source operand in a wider FLEN register must satisfy NaN-boxing rules.
The floating-point result is NaN-boxed in the FLEN register according to the destination format.
RISC-V Unprivileged ISA Manual, Zfh half-precision floating-point extension

Common Usage Scenarios

Device & IO

Understand this scenario with real code like «fcvt.s.h f10, f11 ; f10 = (float)f11».

Type Conversion

Understand this scenario with real code like «fcvt.s.h f10, f11 ; f10 = (float)f11».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This is a floating-point widening conversion, not a narrowing conversion; rm does not affect the numeric result.
The floating-point source operand in a wider FLEN register must satisfy NaN-boxing rules.
The floating-point result is NaN-boxed in the FLEN register according to the destination format.

FAQ

When does rm matter for fcvt.s.h?

It does not matter for the numeric result. This form is an exact widening conversion and does not require rounding.

How does fcvt.s.h differ from related FCVT instructions?

It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.