Which registers does fcvt.s.d use?
rd and rs1 are FP; rs2 encodes the source format.
FCVT.S.D
RISC-V FCVT.S.D Instruction Details
Instruction ManualOP-FPDouble to Single FP; round according to rm when inexact.
Instruction Syntax
fcvt.s.d rd, rs1, rm
rd is FP f0–f31 (f0 is writable); rs1 is FP f0–f31; source/destination may overlap. rs2 selects the source type; no immediate.
32-bit OP-FP: funct5=01000, fmt=00 (destination S), rs2=00001, opcode=1010011.
RV32/RV64; requires D, depending on F. Enable required extensions and FP state.
Optional rm defaults to dyn using frm; static 101/110 and dynamic frm=101–111 have reserved behavior. Inexact conversion rounds using rm and raises NX.
A source narrower than FLEN requires NaN-boxing; an invalid box becomes canonical NaN. S results set all upper bits to ones when FLEN>32. Exceptions accrue in fflags; flag setting alone causes no FP exception trap. Finite animation examples assume initial fflags=0.
DFloating-Point Convert
Instruction Behavior
fcvt.s.d converts a double-precision value in FP rs1 to single precision in FP rd. rm/frm selects rounding; inexact results set NX.
FCVT.S.D Decode And Execute Animation
Shows the D-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the floating-point destination.
rd
rs1
rm
fcvt.s.d
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=S (00)
rs2=D
rounding: RNE nearest-even
fflags: 0
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FCVT.S
00
fmt=S
00001
rs2=D
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x40158553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + 00 -> FCVT.S.D
rs2
00001 -> D source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / fa1(f11)
read
fa1(f11) = D 1.5 (0x3FF8000000000000)
convert
D 1.5 -> S 1.5
write
fa0(f10) = S 1.5 (0x3FC00000); 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0x40158553
syntax : fcvt.s.d fa0(f10), fa1(f11), rne
result : fa0(f10) = S 1.5 (0x3FC00000); 0
D-to-S is a floating-point narrowing conversion; the current example is exactly representable by the target format and leaves fflags at 0.
FCVT Conversion View
D FP source
D 1.5 (0x3FF8000000000000)
conversion
D 1.5 -> S 1.5
writeback
fa0(f10) = S 1.5 (0x3FC00000)
D-to-S is a floating-point narrowing conversion; the current example is exactly representable by the target format and leaves fflags at 0.
This animation shows only D-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
Double to Single FP; round according to rm when inexact.
32-bit OP-FP: funct5=01000, fmt=00 (S), rs2=00001, opcode=1010011.
rd and rs1 are f0–f31; f0 is writable and source/destination may overlap.
A D source requires NaN-boxing when FLEN=128; an invalid box becomes canonical NaN.
RV32/RV64; requires D (depending on F). Enable required extensions and FP state.
Common Usage Scenarios
FP format conversion
Understand this scenario with real code like «# f1 = 16777217; rm=rne; initial fflags=0 fcvt.s.d f0, f1, rne # f0 = 16777216; fflags=NX».
Pre-Use Checklist
Syntax Check
- rd is FP f0–f31 (f0 is writable); rs1 is FP f0–f31; source/destination may overlap. rs2 selects the source type; no immediate.
- 32-bit OP-FP: funct5=01000, fmt=00 (destination S), rs2=00001, opcode=1010011.
Semantic Check
- RV32/RV64; requires D, depending on F. Enable required extensions and FP state.
- Optional rm defaults to dyn using frm; static 101/110 and dynamic frm=101–111 have reserved behavior. Inexact conversion rounds using rm and raises NX.
- A source narrower than FLEN requires NaN-boxing; an invalid box becomes canonical NaN. S results set all upper bits to ones when FLEN>32. Exceptions accrue in fflags; flag setting alone causes no FP exception trap. Finite animation examples assume initial fflags=0.
Pitfalls / Common Confusions
rs2 selects the source type, not a second register operand.
Optional rm defaults to dyn using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
Narrowing can raise NV/OF/UF/NX; FP exception flags accrue rather than automatically clear.
S results set upper bits to ones when FLEN>32; the animation models only its listed finite sources.
FAQ
How does fcvt.s.d use rm?
Inexact conversion rounds using rm and raises NX. Omitted rm defaults to dyn using frm; reserved encoding rules still apply.