When does rm matter for fcvt.s.q?
When the destination format cannot exactly represent the source value, rm or dynamic frm selects the rounding direction.
FCVT.S.Q
RISC-V FCVT.S.Q Instruction Details
Instruction ManualR-typeConvert quad to single FP. May round/overflow/underflow. R-type, fmt=S(00), rs2=source Q(11).
Instruction Syntax
fcvt.s.q rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
QFloating-Point Convert
Instruction Behavior
fcvt.s.q converts a quad-precision source operand to a narrower single-precision result. If the destination format cannot represent the value exactly, the result is rounded according to rm.
Quick Understanding & Search Notes
fcvt.s.q converts a quad-precision source operand to a narrower single-precision result. If the destination format cannot represent the value exactly, the result is rounded according to rm.
The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.
This is a floating-point narrowing conversion and may set overflow, underflow, or inexact exception flags.
The floating-point source operand in a wider FLEN register must satisfy NaN-boxing rules.
The floating-point result is NaN-boxed in the FLEN register according to the destination format.
Common Usage Scenarios
Floating Point Basic
Understand this scenario with real code like «fcvt.s.q f0, f1, rne # f0 = (float)(quad)f1».
Numerical Computing
Understand this scenario with real code like «fcvt.s.q f0, f1, rne # f0 = (float)(quad)f1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
This is a floating-point narrowing conversion and may set overflow, underflow, or inexact exception flags.
The floating-point source operand in a wider FLEN register must satisfy NaN-boxing rules.
The floating-point result is NaN-boxed in the FLEN register according to the destination format.
FAQ
How does fcvt.s.q differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.