Is rs2 a source register in fcvt.q.s?
No. rs2=00000 selects source format S; the assembly operands are rd, rs1, and optional rm.
FCVT.Q.S
RISC-V FCVT.Q.S Instruction Details
Instruction ManualR-typeExactly widen single-precision to quad-precision FP; rm is still decoded normally.
Instruction Syntax
fcvt.q.s rd, rs1[, rm]
rd is FP f0–f31, including writable f0; rs1 is FP f0–f31. rs2 selects the source type; no immediate.
32-bit OP-FP: funct5=01000, fmt=11 (destination Q), rs2=00000, opcode=1010011.
RV32/RV64 Q; Q depends on D, which depends on F. Enable required extensions and FP state. Finite conversion is exact and legal rm leaves the value unchanged.
Optional assembly rm defaults to dyn, using frm; software should select rne (000). Static rm=101/110 and dynamic frm=101–111 have reserved behavior even for exact conversions.
The upper 96 bits of the S source must all be 1; invalid NaN-boxing is treated as a canonical S NaN. rd may overlap rs1: read the original source before writing the Q result.
The Q result fills FLEN=128. Exceptions accrue in fflags; exact finite examples set no new flags and do not clear existing flags. Steps are teaching views.
QFloating-Point Convert
Instruction Behavior
fcvt.q.s converts the single-precision value in FP register rs1 to a quad-precision result in FP register rd. Finite widening is exact, but rm still exists; software should select RNE (000), with normal decoding of legal and reserved encodings.
FCVT.Q.S Decode And Execute Animation
Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the floating-point destination.
rd
rs1
rm
fcvt.q.s
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=Q (11)
rs2=S
rounding: RNE nearest-even
fflags: 0
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FCVT.Q
11
fmt=Q
00000
rs2=S
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x46058553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + 11 -> FCVT.Q.S
rs2
00000 -> S source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / fa1(f11)
read
fa1(f11) = S 1.5 (0x3FC00000)
convert
S 1.5 -> Q 1.5
write
fa0(f10) = Q 1.5 (numeric Q); 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0x46058553
syntax : fcvt.q.s fa0(f10), fa1(f11), rne
result : fa0(f10) = Q 1.5 (numeric Q); 0
S-to-Q is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.
FCVT Conversion View
S FP source
S 1.5 (0x3FC00000)
conversion
S 1.5 -> Q 1.5
writeback
fa0(f10) = Q 1.5 (numeric Q)
S-to-Q is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.
This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.q.s converts the single-precision value in FP register rs1 to a quad-precision result in FP register rd. Finite widening is exact, but rm still exists; software should select RNE (000), with normal decoding of legal and reserved encodings.
32-bit OP-FP: funct5=01000, fmt=11, rs2=00000, opcode=1010011; no immediate.
rd is FP f0–f31; rs1 is FP f0–f31.
RV32/RV64 Q; Q depends on D, which depends on F. Enable required extensions and FP state.
Finite source conversion is exact and legal rm does not change the value. Optional rm defaults to dyn, using frm. Software should select rne (000); static 101/110 and dynamic frm=101–111 have reserved behavior.
With FLEN=128, the upper 96 bits of an S source must all be 1; an invalid box is treated as a canonical S NaN. The Q result fills its destination FP register.
Exception flags accrue in fflags; exact finite examples set no new flags, and this instruction does not clear existing flags.
Common Usage Scenarios
Floating-point format conversion
Understand this scenario with real code like «# f1 contains a correctly NaN-boxed S value 1.5; initial fflags = 0 fcvt.q.s f0, f1, rne # f0 = Q value 1.5 exactly; fflags = 0».
Pre-Use Checklist
Syntax Check
- rd is FP f0–f31, including writable f0; rs1 is FP f0–f31. rs2 selects the source type; no immediate.
- 32-bit OP-FP: funct5=01000, fmt=11 (destination Q), rs2=00000, opcode=1010011.
Semantic Check
- RV32/RV64 Q; Q depends on D, which depends on F. Enable required extensions and FP state. Finite conversion is exact and legal rm leaves the value unchanged.
- Optional assembly rm defaults to dyn, using frm; software should select rne (000). Static rm=101/110 and dynamic frm=101–111 have reserved behavior even for exact conversions.
- The upper 96 bits of the S source must all be 1; invalid NaN-boxing is treated as a canonical S NaN. rd may overlap rs1: read the original source before writing the Q result.
- The Q result fills FLEN=128. Exceptions accrue in fflags; exact finite examples set no new flags and do not clear existing flags. Steps are teaching views.
Pitfalls / Common Confusions
rs2=00000 selects source format S, rather than a second source register; fmt=11 selects destination Q.
Optional rm defaults to dyn, using frm; exact widening still requires normal decoding of legal and reserved rm encodings.
With FLEN=128, the upper 96 bits of an S source must all be 1; an invalid box is treated as a canonical S NaN. The Q result fills its destination FP register.
The animation accepts only the listed finite exact values and assumes valid source NaN-boxing; NaNs, infinities and payload paths are not modeled.
FAQ
When does fcvt.q.s use rm?
Finite widening is exact, so legal rounding modes leave the value unchanged. rm still exists: software should select rne; omission defaults to dyn, using frm. Reserved encodings retain reserved behavior.
How is fcvt.q.s different from integer FCVT forms?
In this form, both rd and rs1 are FP registers; W/WU/L/LU forms convert between integer and FP registers.