Is rs2 a source register in fcvt.q.s?
No. The assembly syntax has rd, rs1 only; the encoded rs2 field selects the source S FP format.
FCVT.Q.S
RISC-V FCVT.Q.S Instruction Details
Instruction ManualR-typeConvert single-precision FP to quad-precision FP; widening conversion is exact and does not use rm.
Instruction Syntax
fcvt.q.s rd, rs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
QFloating-Point Convert
Instruction Behavior
fcvt.q.s reads a single-precision source value from FP register rs1, converts it to a quad-precision FP result, and writes FP register rd. In the OP-FP encoding, fmt=Q (11) denotes the destination format and rs2=S (00) denotes the source format; this widening conversion is exact and has no rm assembly operand.
FCVT.Q.S Decode And Execute Animation
Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, rm rounding, read the floating-point source, then write the floating-point destination.
rd
rs1
fcvt.q.s
,
Execution Context
fmt=Q (11)
rs2=S
rounding: rm not used
fflags: 0
The source value is invalid and is not used for execution. The animation is using a legal FCVT.Q.S default example value.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FCVT.Q
11
fmt=Q
00000
rs2=S
01011
rs1
000
rm=000
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x46058553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + 11 -> FCVT.Q.S
rs2
00000 -> S source
rm
000 -> no rounding operand
rd/rs1
fa0(f10) / fa1(f11)
read
fa1(f11) = S 1.5 (0x3FC00000)
convert
S 1.5 -> Q 1.5
write
fa0(f10) = Q 1.5 (numeric Q); 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT conversion instructions use opcode 1010011.
encoding: 0x46058553
syntax : fcvt.q.s fa0(f10), fa1(f11)
result : fa0(f10) = 1.5; 0
S-to-Q is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.
FCVT Conversion View
S FP source
S 1.5 (0x3FC00000)
conversion
S 1.5 -> Q 1.5
writeback
fa0(f10) = Q 1.5 (numeric Q)
S-to-Q is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.
This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.q.s is an FP-to-FP format conversion: rd and rs1 are FP registers, fmt encodes destination Q, and rs2 encodes source S. The widening conversion is exact and does not use rm.
OP-FP opcode is 1010011; funct5=01000 denotes FP-to-FP format FCVT.
fmt=11 selects destination Q (quad-precision); rs2=00 selects source S (single-precision).
rd and rs1 are both FP registers; the rs2 field is a source-format selector, not an assembly operand.
The widening conversion is exact, requires no rounding, and has no rm in assembly syntax.
NaN-boxing applies to source checking and destination writeback in wider FLEN registers; the animation does not enumerate every NaN payload or special-value combination.
Common Usage Scenarios
Floating-Point Format Conversion
Understand this scenario with real code like «fcvt.q.s f0, f1 # f0 = (quad-precision)(f1 as single-precision)».
Type Conversion
Understand this scenario with real code like «fcvt.q.s f0, f1 # f0 = (quad-precision)(f1 as single-precision)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
fmt=Q selects the destination quad-precision format; rs2=S selects the source single-precision format and is not a second source register.
This is a floating-point widening conversion with exact official semantics; do not add an rm operand in assembly syntax.
The FP source in a wider FLEN register must satisfy NaN-boxing; the result is NaN-boxed according to the destination format.
The animation shows finite checkable examples only; NaNs, infinities, overflow, underflow, and payload details follow the official manual text.
FAQ
When does fcvt.q.s use rm?
It does not. This widening conversion is exact and has no rm assembly operand.
How is fcvt.q.s different from integer FCVT forms?
In this form, both rd and rs1 are FP registers; W/WU/L/LU forms convert between integer and FP registers.