Is rs2 a source register in fcvt.q.h?
No. The assembly syntax has rd, rs1 only; the encoded rs2 field selects the source H FP format.
FCVT.Q.H
RISC-V FCVT.Q.H Instruction Details
Instruction ManualR-typeConvert half-precision FP to quad-precision FP; the widening conversion is exact, the assembly syntax has no rm operand, and software should encode rm as RNE (000).
Instruction Syntax
fcvt.q.h rd, rs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZfhZfhminQFloating-Point Convert
Extension condition: Requires Q and half-precision support from either Zfh or Zfhmin; Q depends on D, and D depends on F. Extension filters find related instructions and do not by themselves describe a complete executable configuration.
Instruction Behavior
fcvt.q.h reads a half-precision source value from FP register rs1, converts it to a quad-precision FP result, and writes FP register rd. In the OP-FP encoding, fmt=Q (11) denotes the destination format and rs2=H (10) denotes the source format; this widening conversion is exact and has no rm assembly operand.
FCVT.Q.H Decode And Execute Animation
Shows the Q + (Zfh or Zfhmin)-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, an rm=000 encoding example, read the floating-point source, then write the floating-point destination.
rd
rs1
fcvt.q.h
,
Execution Context
fmt=Q (11)
rs2=H
rounding: example rm=000; conversion never rounds
fflags: 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FCVT.Q
11
fmt=Q
00010
rs2=H
01011
rs1
000
rm=000 example
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x46258553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + 11 -> FCVT.Q.H
rs2
00010 -> H source
rm
000 -> example encoding; conversion never rounds
rd/rs1
fa0(f10) / fa1(f11)
read
fa1(f11) = H 1.25 (0x3D00)
convert
H 1.25 -> Q 1.25
write
fa0(f10) = Q 1.25 (numeric Q); 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0x46258553
syntax : fcvt.q.h fa0(f10), fa1(f11)
result : fa0(f10) = Q 1.25 (numeric Q); 0
H-to-Q is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.
FCVT Conversion View
H FP source
H 1.25 (0x3D00)
conversion
H 1.25 -> Q 1.25
writeback
fa0(f10) = Q 1.25 (numeric Q)
H-to-Q is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.
This animation shows only Q + (Zfh or Zfhmin)-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.q.h is an FP-to-FP format conversion: rd and rs1 are FP registers, fmt encodes destination Q, and rs2 encodes source H. The widening conversion is exact, the assembly syntax has no rm operand, and software should encode rm as RNE (000).
OP-FP opcode is 1010011; funct5=01000 denotes FP-to-FP format FCVT.
fmt=11 selects destination Q (quad-precision); rs2=10 selects source H (half-precision).
rd and rs1 are both FP registers; the rs2 field is a source-format selector, not an assembly operand.
Zfhmin combined with Q supports this H/Q conversion.
The widening conversion is exact and needs no numerical rounding; its assembly syntax has no rm operand, software should encode rm as RNE (000), and implementations still distinguish legal and reserved encodings.
With Q, FLEN=128: NaN-boxing checks the H source, while the Q destination is FLEN-wide rather than a narrower boxed writeback. The animation does not enumerate every NaN payload or special-value combination.
Common Usage Scenarios
Floating-Point Format Conversion
Understand this scenario with real code like «fcvt.q.h f0, f1 # f0 = (quad-precision)(f1 as half-precision)».
Type Conversion
Understand this scenario with real code like «fcvt.q.h f0, f1 # f0 = (quad-precision)(f1 as half-precision)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
fmt=Q selects the destination quad-precision format; rs2=H selects the source half-precision format and is not a second source register.
Zfhmin combined with Q supports this H/Q conversion.
This is a floating-point widening conversion with exact official semantics; do not add an rm operand in assembly syntax.
With Q, FLEN=128: the H source must be validly NaN-boxed, while the Q destination is FLEN-wide rather than a narrower NaN-boxed result.
The animation shows finite checkable examples only; NaNs, infinities, overflow, underflow, and payload details follow the official manual text.
FAQ
Which extensions are required for fcvt.q.h?
It requires Q and half-precision support supplied by either Zfh or Zfhmin. Q depends on D, and D depends on F.
When does fcvt.q.h use rm?
The assembly syntax has no rm operand and the exact widening result is unaffected by rounding mode; software should set the machine encoding's rm to RNE (000), while implementations still treat reserved values as reserved encodings.
How is fcvt.q.h different from integer FCVT forms?
In this form, both rd and rs1 are FP registers; W/WU/L/LU forms convert between integer and FP registers.