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FCVT.Q.D

RISC-V FCVT.Q.D Instruction Details

Instruction ManualR-type

Convert double-precision FP to quad-precision FP. RV32/RV64 Q.

Instruction Syntax

fcvt.q.d rd, rs1[, rm]

rd selects FP f0–f31, including writable f0; rs1 selects FP f0–f31; rs2 is a format selector, not a second source register.

32-bit OP-FP: funct5=01000, fmt=11, rs2=00001, opcode=1010011; no immediate.

RV32/RV64 Q; enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior. Finite widening is exact; software should select rne, and legal modes leave the value unchanged.

Check NaN-boxing for a D source narrower than FLEN; an invalid box becomes a canonical source-format NaN. The Q target is full width; overlapping registers read the original source. Exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.

QFloating-Point Convert

Related Search Terms

fcvt.q.d instruction double-precision to quad-precision FP OP-FP encoding rm rounding exact widening NaN-boxing

Instruction Behavior

fcvt.q.d reads a double-precision value from FP register rs1, widens it exactly to Q, and writes FP register rd; legal rounding modes do not change finite results.

FCVT.Q.D Decode And Execute Animation

Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the floating-point destination.

rs1

fcvt.q.d

Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.

Execution Context

fmt=Q (11)

rs2=D

rounding: RNE nearest-even

fflags: 0

Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.

fa1(f11) source valueFinite exact examples: 0, -0, 1, -1, 1.25, -1.5, 2, 3.5, 9; other decimals are outside this demo. Special values are not modeled.

31..27

26..25

24..20

19..15

14..12

11..7

6..0

01000

FCVT.Q

fmt=Q

00001

rs2=D

01011

rs1

000

01010

1010011

OP-FP

Execution Data Path

instruction

0x46158553

opcode

1010011 -> OP-FP

funct5/fmt

01000 + 11 -> FCVT.Q.D

rs2

00001 -> D source

000 -> RNE nearest-even

rd/rs1

fa0(f10) / fa1(f11)

read

fa1(f11) = D 1.25 (0x3FF4000000000000)

convert

D 1.25 -> Q 1.25

write

fa0(f10) = Q 1.25 (numeric Q); 0

Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.

encoding: 0x46158553

syntax : fcvt.q.d fa0(f10), fa1(f11), rne

result : fa0(f10) = Q 1.25 (numeric Q); 0

D-to-Q is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.

FCVT Conversion View

D FP source

D 1.25 (0x3FF4000000000000)

conversion

D 1.25 -> Q 1.25

writeback

fa0(f10) = Q 1.25 (numeric Q)

D-to-Q is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.

This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.

Quick Understanding & Search Notes

fcvt.q.d reads a double-precision value from FP register rs1, widens it exactly to Q, and writes FP register rd; legal rounding modes do not change finite results.

RV32/RV64 Q. Enable required extensions and FP state.

32-bit OP-FP: funct5=01000, fmt=11 selects Q, rs2=00001 selects source D, opcode=1010011; rs2 is not a source register, and there is no immediate.

Optional rm defaults to dyn (111), using frm; static 101/110 and dynamic frm=101–111 have reserved behavior. Widening still encodes rm; software should select RNE (000).

With Q, FLEN=128: the D source must be NaN-boxed or is treated as a canonical source-format NaN. The Q target occupies full width, without upper boxing bits.

Finite widening is exact and does not set NX. NaN results are canonical NaNs; sNaN sets NV. Conversion is not a NaN-payload bit move.

Both rd and rs1 select f0–f31, including writable f0; overlapping operands read the original source. The animation computes only listed finite exact examples and excludes special-value paths.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Q 2.2 The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F 2.2: rounding and conversion The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — D 2.2: NaN Boxing RISC-V Assembly Programmer’s Manual — Floating-point rounding modes

Common Usage Scenarios

Floating-point widening

Understand this scenario with real code like «# f1=1.25; valid D NaN-boxing; fflags=0 fcvt.q.d f0, f1, rne # f0=1.25 (Q); fflags=0».

Pre-Use Checklist

Syntax Check

rd selects FP f0–f31, including writable f0; rs1 selects FP f0–f31; rs2 is a format selector, not a second source register.
32-bit OP-FP: funct5=01000, fmt=11, rs2=00001, opcode=1010011; no immediate.

Semantic Check

RV32/RV64 Q; enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior. Finite widening is exact; software should select rne, and legal modes leave the value unchanged.
Check NaN-boxing for a D source narrower than FLEN; an invalid box becomes a canonical source-format NaN. The Q target is full width; overlapping registers read the original source. Exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.

Pitfalls / Common Confusions