Is rs2 a source register in fcvt.d.q?
No. The assembly syntax has rd, rs1, rm only; the encoded rs2 field selects the source Q FP format.
FCVT.D.Q
RISC-V FCVT.D.Q Instruction Details
Instruction ManualR-typeConvert quad-precision FP to double-precision FP; narrowing conversion rounds according to rm.
Instruction Syntax
fcvt.d.q rd, rs1, rm
Operand Breakdown
rd: destination double-precision FP register; rs1: source quad-precision FP register.
rm: rounding-mode operand; rm=111 uses frm. Encoded fmt=01 selects destination D and rs2=00011 selects source Q.
rs2 is a source-format selector, not a second assembly source register; rm/frm determines rounding when the Q value is not exactly representable as D.
QFloating-Point Convert
Instruction Behavior
fcvt.d.q reads a quad-precision source value from FP register rs1, converts it to a double-precision FP result, and writes FP register rd. In the OP-FP encoding, fmt=D (01) denotes the destination format and rs2=Q (11) denotes the source format; this narrowing conversion rounds according to rm/frm when the destination format cannot represent the source exactly and may set FP exception flags.
FCVT.D.Q Decode And Execute Animation
Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the floating-point destination.
rd
rs1
rm
fcvt.d.q
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=D (01)
rs2=Q
rounding: RNE nearest-even
fflags: 0
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FCVT.D
01
fmt=D
00011
rs2=Q
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x42358553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + 01 -> FCVT.D.Q
rs2
00011 -> Q source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / fa1(f11)
read
fa1(f11) = Q 1.25 (numeric Q)
convert
Q 1.25 -> D 1.25
write
fa0(f10) = D 1.25 (0x3FF4000000000000); 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0x42358553
syntax : fcvt.d.q fa0(f10), fa1(f11), rne
result : fa0(f10) = D 1.25 (0x3FF4000000000000); 0
Q-to-D is a floating-point narrowing conversion; the animation accepts only finite examples exactly representable by the target format, so this example leaves fflags at 0. Inexact, overflow, underflow, NaN, and infinity paths are covered by the static text.
FCVT Conversion View
Q FP source
Q 1.25 (numeric Q)
conversion
Q 1.25 -> D 1.25
writeback
fa0(f10) = D 1.25 (0x3FF4000000000000)
Q-to-D is a floating-point narrowing conversion; the animation accepts only finite examples exactly representable by the target format, so this example leaves fflags at 0. Inexact, overflow, underflow, NaN, and infinity paths are covered by the static text.
This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.d.q is an FP-to-FP format conversion: rd and rs1 are FP registers, fmt encodes destination D, and rs2 encodes source Q. The narrowing conversion rounds according to rm/frm and may set FP exception flags such as NX, OF, or UF.
OP-FP opcode is 1010011; funct5=01000 denotes FP-to-FP format FCVT.
fmt=01 selects destination D (double-precision); rs2=11 selects source Q (quad-precision).
rd and rs1 are both FP registers; the rs2 field is a source-format selector, not an assembly operand.
The Q extension depends on D and extends FLEN to 128.
The narrowing conversion rounds according to rm or dynamic frm when needed and records applicable FP exception flags in fflags.
The Q source is FLEN-wide, so it has no narrower-source NaN-boxing check; the D result is NaN-boxed as D in a Q implementation with FLEN=128. The animation does not enumerate every NaN payload or special-value combination.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Q, Version 2.2The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — D, Version 2.2The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F, Version 2.2RISC-V Assembly Programmer's Manual — Floating-point rounding modes
Common Usage Scenarios
Floating-Point Format Conversion
Understand this scenario with real code like «fcvt.d.q f0, f1, rne # f0 = (double-precision)(f1 as quad-precision)».
Type Conversion
Understand this scenario with real code like «fcvt.d.q f0, f1, rne # f0 = (double-precision)(f1 as quad-precision)».
Pre-Use Checklist
Syntax Check
- rd and rs1 both select f0–f31; encoded fmt selects destination D and rs2 selects the source format, not a source register.
- rm=111 uses frm; narrowing uses a legal rm/frm mode when rounding is needed.
Semantic Check
- Confirm required extensions and enabled FP state; accessing FP state with FS=Off raises an illegal-instruction exception.
- Check source NaN-boxing when narrower than FLEN; write upper ones for a narrower destination. Conversion exception flags accrue in fflags.
Pitfalls / Common Confusions
fmt=D selects the destination double-precision format; rs2=Q selects the source quad-precision format and is not a second source register.
This is a floating-point narrowing conversion; rm or dynamic frm selects rounding when the destination format cannot represent the source exactly.
The Q source is FLEN-wide, so it has no narrower-source NaN-boxing check; the D result is NaN-boxed as D in a Q implementation with FLEN=128.
The animation shows exactly representable finite values only. Actual conversion sets NV and returns canonical NaN for sNaN; qNaN returns canonical NaN. Inexact conversion rounds by rm and accrues applicable NX, OF, and UF flags.
FAQ
When does fcvt.d.q use rm?
When the destination format cannot exactly represent the source value, rm or dynamic frm selects the rounding direction.
How is fcvt.d.q different from integer FCVT forms?
In this form, both rd and rs1 are FP registers; W/WU/L/LU forms convert between integer and FP registers.