Is rs2 a source register in fcvt.d.s?
No. rd and rs1 are FP registers; an optional rounding operand controls rm, whereas encoded rs2 selects source S format.
FCVT.D.S
RISC-V FCVT.D.S Instruction Details
Instruction ManualR-typeConvert single-precision FP to double-precision FP; finite widening is exact and unaffected by legal rounding modes.
Instruction Syntax
fcvt.d.s rd, rs1, rm
Operand Breakdown
rd: destination double-precision FP register; rs1: source single-precision FP register.
Encoded fmt=01 selects destination D and rs2=00000 selects source S; rs2 is not a second assembly source register.
Finite widening is exact and unaffected by legal rounding modes; rm remains encoded, software should select RNE (000), and reserved encoding rules still apply.
DFloating-Point Convert
Instruction Behavior
fcvt.d.s reads a single-precision source value from FP register rs1, converts it to a double-precision FP result, and writes FP register rd. In the OP-FP encoding, fmt=D (01) denotes the destination format and rs2=S (00) denotes the source format; finite widening is exact; rm remains encoded, software should select RNE (000), and legal/reserved encoding rules still apply.
FCVT.D.S Decode And Execute Animation
Shows the D-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the floating-point destination.
rd
rs1
rm
fcvt.d.s
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=D (01)
rs2=S
rounding: RNE nearest-even
fflags: 0
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FCVT.D
01
fmt=D
00000
rs2=S
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x42058553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + 01 -> FCVT.D.S
rs2
00000 -> S source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / fa1(f11)
read
fa1(f11) = S 1.5 (0x3FC00000)
convert
S 1.5 -> D 1.5
write
fa0(f10) = D 1.5 (0x3FF8000000000000); 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0x42058553
syntax : fcvt.d.s fa0(f10), fa1(f11), rne
result : fa0(f10) = D 1.5 (0x3FF8000000000000); 0
S-to-D is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.
FCVT Conversion View
S FP source
S 1.5 (0x3FC00000)
conversion
S 1.5 -> D 1.5
writeback
fa0(f10) = D 1.5 (0x3FF8000000000000)
S-to-D is a floating-point widening conversion; the current finite example is exact, does not need rm rounding, and leaves example fflags at 0.
This animation shows only D-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.d.s is an FP-to-FP format conversion: rd and rs1 are FP registers, fmt encodes destination D, and rs2 encodes source S. The finite widening is exact and unaffected by legal rounding modes.
OP-FP opcode is 1010011; funct5=01000 denotes FP-to-FP format FCVT.
fmt=01 selects destination D (double-precision); rs2=00 selects source S (single-precision).
rd and rs1 are both FP registers; the rs2 field is a source-format selector, not an assembly operand.
The D extension depends on F.
Finite widening is exact and needs no numeric rounding; rm remains encoded and software should select RNE (000). An instruction with rm can take a lowercase rounding operand; omission defaults to dyn in assembly.
When the source or destination format is narrower than FLEN, check source NaN-boxing or fill destination upper bits with ones, respectively. Invalid boxing is treated as canonical NaN. Converting sNaN sets NV; a NaN result is canonical NaN. The animation demonstrates finite values only.
Common Usage Scenarios
Floating-Point Format Conversion
Understand this scenario with real code like «fcvt.d.s f0, f1, rne # f0 = (double-precision)(f1 as single-precision)».
Type Conversion
Understand this scenario with real code like «fcvt.d.s f0, f1, rne # f0 = (double-precision)(f1 as single-precision)».
Pre-Use Checklist
Syntax Check
- rd and rs1 both select f0–f31; encoded fmt selects destination D and rs2 selects the source format, not a source register.
- rm=111 uses frm; use legal rounding modes. Exact widening still has rm, and software should select RNE.
Semantic Check
- Confirm required extensions and enabled FP state; accessing FP state with FS=Off raises an illegal-instruction exception.
- Check source NaN-boxing when narrower than FLEN; write upper ones for a narrower destination. Conversion exception flags accrue in fflags.
Pitfalls / Common Confusions
fmt=D selects the destination double-precision format; rs2=S selects the source single-precision format and is not a second source register.
Finite widening needs no rounding; rm still exists and software should select RNE (000). Reserved rm encodings are not legal encodings.
The FP source in a wider FLEN register must satisfy NaN-boxing; the result is NaN-boxed according to the destination format.
The animation shows finite checkable examples only; NaNs, infinities, overflow, underflow, and payload details follow the official manual text.
FAQ
When does fcvt.d.s use rm?
Legal rounding modes do not affect the finite numeric result, but rm remains encoded. Software should select RNE (000); reserved-rounding encoding rules still apply.
How is fcvt.d.s different from integer FCVT forms?
In this form, both rd and rs1 are FP registers; W/WU/L/LU forms convert between integer and FP registers.