When is conversion invalid?
Round before checking 0..2^64−1; below-range values or −infinity yield 0, while above-range values, +infinity, or any NaN yield 2^64−1, setting NV.
FCVT.LU.Q
RISC-V FCVT.LU.Q Instruction Details
Instruction ManualR-typeConvert quad-precision FP to unsigned 64-bit integer. RV64 Q only.
Instruction Syntax
fcvt.lu.q rd, rs1[, rm]
rd selects integer x0–x31; x0 discards results without suppressing fflags; rs1 selects FP f0–f31; rs2 is a format selector, not a second source register.
32-bit OP-FP: funct5=11000, fmt=11, rs2=00011, opcode=1010011; no immediate.
RV64 Q only; enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior. Round before checking integer range; invalid sets NV, otherwise inexact sets NX.
A Q source occupies full FLEN=128, without narrower-source boxing checks. Integer results are not boxed. Exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.
QFloating-Point Convert
Instruction Behavior
fcvt.lu.q reads a quad-precision value from FP register rs1, rounds it to a unsigned 64-bit integer using rm/frm, and writes integer register rd.
FCVT.LU.Q Decode And Execute Animation
Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.lu.q
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=Q (11)
rs2=LU
rounding: RNE nearest-even
fflags: NX
RV64-only
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.LU
11
fmt=Q
00011
rs2=LU
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC6358553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 11 -> FCVT.LU.Q
rs2
00011 -> LU target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = 3.5
convert
3.5 -> uint64 0x00000004 (4)
write
a0(x10) = 4; NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xC6358553
syntax : fcvt.lu.q a0(x10), fa1(f11), rne
result : a0(x10) = 4; NX
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
Q FP source
3.5
conversion
3.5 -> uint64 0x00000004 (4)
writeback
a0(x10) = 4
The current example rounds to a 64-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.lu.q reads a quad-precision value from FP register rs1, rounds it to a unsigned 64-bit integer using rm/frm, and writes integer register rd.
RV64 Q only. Enable required extensions and FP state.
32-bit OP-FP: funct5=11000, fmt=11 selects Q, rs2=00011 selects unsigned LU, opcode=1010011; rs2 is not a source register, and there is no immediate.
Optional rm defaults to dyn (111), using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
Round before checking 0..2^64−1; below-range values or −infinity yield 0, while above-range values, +infinity, or any NaN yield 2^64−1, setting NV.
Set NX only if the result differs from the source and NV is not set. Exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.
A Q source occupies full FLEN=128, so no narrower-source NaN-boxing check applies. rd=x0 discards the integer result without suppressing exception flags.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Q 2.2The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F 2.2: rounding and conversionThe RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — D 2.2: NaN BoxingRISC-V Assembly Programmer’s Manual — Floating-point rounding modes
Common Usage Scenarios
Floating-point to integer conversion
Understand this scenario with real code like «# RV64; f1=3.5; fflags=0 fcvt.lu.q x10, f1, rtz # x10=3; NX».
Pre-Use Checklist
Syntax Check
- rd selects integer x0–x31; x0 discards results without suppressing fflags; rs1 selects FP f0–f31; rs2 is a format selector, not a second source register.
- 32-bit OP-FP: funct5=11000, fmt=11, rs2=00011, opcode=1010011; no immediate.
Semantic Check
- RV64 Q only; enable required extensions and FP state. Optional rm defaults to dyn, using frm; static 101/110 and dynamic frm=101–111 have reserved behavior. Round before checking integer range; invalid sets NV, otherwise inexact sets NX.
- A Q source occupies full FLEN=128, without narrower-source boxing checks. Integer results are not boxed. Exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.
Pitfalls / Common Confusions
RV64 Q only. Enable required extensions and FP state.
Optional rm defaults to dyn (111), using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
Round before checking 0..2^64−1; below-range values or −infinity yield 0, while above-range values, +infinity, or any NaN yield 2^64−1, setting NV.
Set NX only if the result differs from the source and NV is not set. Exceptions accrue in fflags; setting a flag does not itself cause an FP exception trap.
A Q source occupies full FLEN=128, so no narrower-source NaN-boxing check applies. rd=x0 discards the integer result without suppressing exception flags.
FAQ
Does writing x0 suppress exceptions?
No. Only the integer writeback is discarded; NV or NX still accrues according to the source and rounded result.