When does rm matter for fcvt.lu.q?
When conversion requires rounding, rm or dynamic frm selects the rounding direction; out-of-range or NaN inputs follow the official invalid-conversion rule.
FCVT.LU.Q
RISC-V FCVT.LU.Q Instruction Details
Instruction ManualR-typeConvert quad FP to unsigned 64-bit int [RV64]. R-type, fmt=LU(11), rs2=source Q(11).
Instruction Syntax
fcvt.lu.q rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
QFloating-Point Convert
Instruction Behavior
fcvt.lu.q converts a quad-precision source operand to an unsigned 64-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
Quick Understanding & Search Notes
fcvt.lu.q converts a quad-precision source operand to an unsigned 64-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.
L/LU 64-bit integer result forms are RV64-only.
Out-of-range integer targets or NaN inputs follow the official invalid floating-point-to-integer conversion rules and set NV.
Floating-point source operands in wider FLEN registers must satisfy NaN-boxing rules.
Common Usage Scenarios
Floating Point Basic
Understand this scenario with real code like «fcvt.lu.q x10, f0, rtz # x10 = (ulong)f0 (RV64)».
Numerical Computing
Understand this scenario with real code like «fcvt.lu.q x10, f0, rtz # x10 = (ulong)f0 (RV64)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
L/LU 64-bit integer result forms are RV64-only.
Out-of-range integer targets or NaN inputs follow the official invalid floating-point-to-integer conversion rules and set NV.
Floating-point source operands in wider FLEN registers must satisfy NaN-boxing rules.
FAQ
How does fcvt.lu.q differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.