When does rm matter for fcvt.w.q?
When conversion requires rounding, rm or dynamic frm selects the rounding direction; out-of-range or NaN inputs follow the official invalid-conversion rule.
FCVT.W.Q
RISC-V FCVT.W.Q Instruction Details
Instruction ManualOP-FP conversion fieldsConvert quad FP to signed 32-bit int: fmt=Q (11) selects the FP source and rs2=W (00000) selects the signed integer target.
Instruction Syntax
fcvt.w.q rd, rs1, rm
Operand Breakdown
This is a OP-FP conversion fields-format instruction. Confirm operand positions based on the assembly syntax.
QFloating-Point Convert
Instruction Behavior
fcvt.w.q converts a quad-precision source operand to a signed 32-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
FCVT.W.Q Decode And Execute Animation
Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.w.q
,
,
Execution Context
fmt=Q (11)
rs2=W
rounding: RNE nearest-even
fflags: NX
The source value is invalid and is not used for execution. The animation is using a legal FCVT.W.Q default example value.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.W
11
fmt=Q
00000
rs2=W
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC6058553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 11 -> FCVT.W.Q
rs2
00000 -> W target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = -42.75
convert
-42.75 -> int32 -43
write
a0(x10) = 0xFFFFFFD5 (-43); NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xC6058553
syntax : fcvt.w.q a0(x10), fa1(f11), rne
result : a0(x10) = 0xFFFFFFD5 (-43); NX
The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
Q FP source
-42.75
conversion
-42.75 -> int32 -43
writeback
a0(x10) = 0xFFFFFFD5 (-43)
The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.w.q converts a quad-precision source operand to a signed 32-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
The OP-FP opcode is 1010011; funct5=11000 denotes FP-to-integer FCVT and fmt=11 denotes the Q source format.
rs2=00000 selects the W signed 32-bit integer target; rm selects static rounding or DYN/frm.
Negative out-of-range inputs or -infinity write -2^31; positive out-of-range inputs, +infinity, or NaN write 2^31-1 and set NV.
The W 32-bit result is sign-extended to XLEN on RV64; a Q source is FLEN=128 and is not a narrower NaN-boxed value.
Common Usage Scenarios
Floating Point Basic
Understand this scenario with real code like «fcvt.w.q x10, f0, rtz # x10 = (int)f0».
Numerical Computing
Understand this scenario with real code like «fcvt.w.q x10, f0, rtz # x10 = (int)f0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OP-FP conversion fields.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
On RV64, the W 32-bit result is sign-extended to XLEN in the integer register.
For signed W, negative out-of-range inputs or -infinity write -2^31; positive out-of-range inputs, +infinity, or NaN write 2^31-1 and set NV.
Q is the FLEN=128 source format; this Q operand is not a narrower NaN-boxed value in a wider FP register.
FAQ
How does fcvt.w.q differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.