Can rm be omitted?
Yes; it defaults to dyn and uses frm.
FCVT.W.Q
RISC-V FCVT.W.Q Instruction Details
Instruction ManualOP-FP conversion fieldsRound a quad-precision source using rm to a signed 32-bit integer; RV64 sign-extends bit 31 to XLEN.
Instruction Syntax
fcvt.w.q rd, rs1[, rm]
rd is integer x0–x31; rs1 is FP f0–f31 (ABI names accepted). x10 and f10 are different registers. rs2 selects integer type; no immediate. rd=x0 discards only the integer result; NV/NX still accrue in fflags.
32-bit OP-FP: funct5=11000, fmt=11 (FP source), rs2=00000 (W), opcode=1010011.
RV32/RV64; requires Q (D, F). Enable required extensions and FP state. Optional rm defaults to dyn using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
Round using rm before testing the -2^31..2^31-1 range. Negative out-of-range/-infinity yields -2^31; positive out-of-range/+infinity/NaN yields 2^31-1 and sets NV. A changed result sets NX only without NV. RV64 sign-extends bit 31, including WU.
The Q source has FLEN=128 and is not a narrower boxed value. Exception flags accrue in fflags; flag setting alone causes no FP exception trap. Animation assumes valid applicable NaN-boxing and initial fflags=0; numeric previews commit at Writeback.
QFloating-Point Convert
Instruction Behavior
fcvt.w.q converts a quad-precision source operand to a signed 32-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
FCVT.W.Q Decode And Execute Animation
Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.w.q
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=Q (11)
rs2=W
rounding: RNE nearest-even
fflags: NX
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.W
11
fmt=Q
00000
rs2=W
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC6058553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 11 -> FCVT.W.Q
rs2
00000 -> W target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = -1.5
convert
-1.5 -> int32 -2
write
a0(x10) = 0xFFFFFFFE (-2); NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xC6058553
syntax : fcvt.w.q a0(x10), fa1(f11), rne
result : a0(x10) = 0xFFFFFFFE (-2); NX
The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
Q FP source
-1.5
conversion
-1.5 -> int32 -2
writeback
a0(x10) = 0xFFFFFFFE (-2)
The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.w.q converts a quad-precision source operand to a signed 32-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
The OP-FP opcode is 1010011; funct5=11000 denotes FP-to-integer FCVT and fmt=11 denotes the Q source format.
rs2=00000 selects the W signed 32-bit integer target; rm selects static rounding or DYN/frm.
Negative out-of-range inputs or -infinity write -2^31; positive out-of-range inputs, +infinity, or NaN write 2^31-1 and set NV.
The W 32-bit result is sign-extended to XLEN on RV64; a Q source is FLEN=128 and is not a narrower NaN-boxed value.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — §§21.2, 21.7, Table 27The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — §23.3RISC-V Assembly Programmer's Manual, Version v0.0.0 (2025-02-05; release v0.0.1) — Floating-point rounding modes
Common Usage Scenarios
Quad-Precision to signed 32-bit integer conversion
Understand this scenario with real code like «fcvt.w.q x10, f11, rtz # f11=1.5 -> x10=1; fflags=NX # RV32/RV64; required extensions and FP state enabled # Valid NaN-boxing when required; initial fflags=0».
Pre-Use Checklist
Syntax Check
- rd is integer x0–x31; rs1 is FP f0–f31 (ABI names accepted). x10 and f10 are different registers. rs2 selects integer type; no immediate. rd=x0 discards only the integer result; NV/NX still accrue in fflags.
- 32-bit OP-FP: funct5=11000, fmt=11 (FP source), rs2=00000 (W), opcode=1010011.
Semantic Check
- RV32/RV64; requires Q (D, F). Enable required extensions and FP state. Optional rm defaults to dyn using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
- Round using rm before testing the -2^31..2^31-1 range. Negative out-of-range/-infinity yields -2^31; positive out-of-range/+infinity/NaN yields 2^31-1 and sets NV. A changed result sets NX only without NV. RV64 sign-extends bit 31, including WU.
- The Q source has FLEN=128 and is not a narrower boxed value. Exception flags accrue in fflags; flag setting alone causes no FP exception trap. Animation assumes valid applicable NaN-boxing and initial fflags=0; numeric previews commit at Writeback.
Pitfalls / Common Confusions
On RV64, the W 32-bit result is sign-extended to XLEN in the integer register.
For signed W, negative out-of-range inputs or -infinity write -2^31; positive out-of-range inputs, +infinity, or NaN write 2^31-1 and set NV.
Q is the FLEN=128 source format; this Q operand is not a narrower NaN-boxed value in a wider FP register.
FAQ
When are NV and NX set?
Check the range after rounding. Invalid conversion sets NV; a result differing from the source sets NX only without NV.