When does rm matter for fcvt.w.d?
When conversion requires rounding, rm or dynamic frm selects the rounding direction; out-of-range or NaN inputs follow the official invalid-conversion rule.
FCVT.W.D
RISC-V FCVT.W.D Instruction Details
Instruction ManualR-typeConvert double to signed int32: rd = (int32_t)f[rs1].
Instruction Syntax
fcvt.w.d rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
DFloating-Point Convert
Instruction Behavior
fcvt.w.d converts a double-precision source operand to a signed 32-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
Quick Understanding & Search Notes
fcvt.w.d converts a double-precision source operand to a signed 32-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.
W/WU 32-bit integer results are extended to XLEN on RV64 according to the official rules.
Out-of-range integer targets or NaN inputs follow the official invalid floating-point-to-integer conversion rules and set NV.
Floating-point source operands in wider FLEN registers must satisfy NaN-boxing rules.
Common Usage Scenarios
Type Conversion
Understand this scenario with real code like «fcvt.w.d x10, f0, rtz # x10 = (int)f0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
W/WU 32-bit integer results are extended to XLEN on RV64 according to the official rules.
Out-of-range integer targets or NaN inputs follow the official invalid floating-point-to-integer conversion rules and set NV.
Floating-point source operands in wider FLEN registers must satisfy NaN-boxing rules.
FAQ
How does fcvt.w.d differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.