Which register classes do rd and rs1 use in fcvt.wu.d?
This is a floating-point-to-integer conversion: rs1 is a floating-point register and rd is an integer register.
FCVT.WU.D
RISC-V FCVT.WU.D Instruction Details
Instruction ManualR-typeConvert double to unsigned int32: rd = (uint32_t)f[rs1].
Instruction Syntax
fcvt.wu.d rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
DFloating-Point Convert
Instruction Behavior
fcvt.wu.d converts a double-precision source operand to an unsigned 32-bit integer result. Floating-point-to-integer conversion rounds according to rm and writes integer register rd.
FCVT.WU.D Decode And Execute Animation
Shows the D-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, rm rounding, read the floating-point source, then write the integer destination.
rd
rs1
rm
fcvt.wu.d
,
,
Execution Context
fmt=WU (00)
rs2=WU
rounding: RNE nearest-even
fflags: NX
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11000
FCVT.WU
00
fmt=WU
00001
rs2=WU
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xC0158553
opcode
1010011 -> OP-FP
funct5/fmt
11000 + 00 -> FCVT.WU.D
rs2
00001 -> WU target
rm
000 -> RNE nearest-even
rd/rs1
a0(x10) / fa1(f11)
read
fa1(f11) = 42.75
convert
42.75 -> uint32 0x0000002B (43)
write
a0(x10) = 0x0000002B (43); NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT conversion instructions use opcode 1010011.
encoding: 0xC0158553
syntax : fcvt.wu.d a0(x10), fa1(f11), rne
result : a0(x10) = 0x0000002B (43); NX
The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.
FCVT Conversion View
D FP source
42.75
conversion
42.75 -> uint32 0x0000002B (43)
writeback
a0(x10) = 0x0000002B (43)
The current example rounds to a 32-bit integer according to rm and shows NX because the source has a fractional part.
This animation shows only D-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.wu.d reads a double-precision FP source in rs1, rounds it according to rm to an unsigned 32-bit integer, and writes x[rd]; negative, NaN, or out-of-range uint32 inputs take the official invalid-conversion path.
OP-FP opcode is 1010011; funct5=11000 denotes FP-to-integer FCVT and fmt=01 denotes D source format.
rs2=00001 selects the WU unsigned 32-bit integer target; rm controls rounding.
rd is an integer register and rs1 is a double-precision FP register; the result is not an FP encoding.
Inexact conversion sets NX; NaN, negative, or out-of-range uint32 inputs set NV by the official rule.
W/WU results are extended to XLEN on RV64 according to the official rule.
Common Usage Scenarios
Type Conversion
Understand this scenario with real code like «fcvt.wu.d x10, f0, rtz # x10 = (unsigned)f0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
W/WU 32-bit integer results are extended to XLEN on RV64 according to the official rules.
Out-of-range integer targets or NaN inputs follow the official invalid floating-point-to-integer conversion rules and set NV.
Floating-point source operands in wider FLEN registers must satisfy NaN-boxing rules.
FAQ
When does rm affect fcvt.wu.d?
When the FP source is not integral and must be rounded to an integer, rm affects the 32-bit integer written to rd; inexact conversion sets NX. NaN or out-of-range inputs follow the official invalid-conversion rule and set NV.
What does the rs2 field select in fcvt.wu.d?
rs2 is not an ordinary source register; in the FCVT encoding it selects the WU unsigned 32-bit integer format.