Which register classes do rd and rs1 use in fcvt.d.wu?
This is an integer-to-floating-point conversion: rs1 is an integer register and rd is a floating-point register.
FCVT.D.WU
RISC-V FCVT.D.WU Instruction Details
Instruction ManualR-typeConvert unsigned int32 to double: f[rd] = (double)(uint32_t)rs1. Always exact.
Instruction Syntax
fcvt.d.wu rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
DFloating-Point Convert
Instruction Behavior
fcvt.d.wu converts an unsigned 32-bit integer source to a double-precision floating-point result. This conversion is exact, so the encoded rounding mode does not change the numeric result.
FCVT.D.WU Decode And Execute Animation
Shows the D-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, rm rounding, read the integer source, then write the floating-point destination.
rd
rs1
rm
fcvt.d.wu
,
,
Execution Context
fmt=D (01)
rs2=WU
rounding: RNE nearest-even
fflags: 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11010
FCVT.D
01
fmt=D
00001
rs2=WU
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xD2158553
opcode
1010011 -> OP-FP
funct5/fmt
11010 + 01 -> FCVT.D.WU
rs2
00001 -> WU source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / a1(x11)
read
a1(x11) = 0xFFFFFFFF (4294967295)
convert
uint32 0xFFFFFFFF (4294967295) -> D 4294967295.0
write
fa0(f10) = 4294967295.0; 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT conversion instructions use opcode 1010011.
encoding: 0xD2158553
syntax : fcvt.d.wu fa0(f10), a1(x11), rne
result : fa0(f10) = 4294967295.0; 0
A 32-bit integer is exactly representable as double precision, so example fflags remains 0.
FCVT Conversion View
WU source
0xFFFFFFFF (4294967295)
conversion
uint32 0xFFFFFFFF (4294967295) -> D 4294967295.0
writeback
fa0(f10) = 4294967295.0
A 32-bit integer is exactly representable as double precision, so example fflags remains 0.
This animation shows only D-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.d.wu reads an unsigned 32-bit integer from integer register rs1, converts it to double precision, and writes f[rd]; uint32 is exactly representable as double, so the numeric result does not depend on rm.
OP-FP opcode is 1010011; funct5=11010 denotes integer-to-FP FCVT and fmt=01 denotes D destination format.
rs2=00001 selects the WU unsigned 32-bit integer source; rs1 is an integer register.
rd is an FP register and the result is written in D format; uint32 to double conversion is exact.
rm is still encoded, but it does not affect this uint32 to double numeric result.
The instruction does not read an FP source register, so there is no source NaN-boxing requirement.
Common Usage Scenarios
Type Conversion
Understand this scenario with real code like «fcvt.d.wu f0, x10, rne # f0 = (double)(unsigned)x10».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
W/WU forms read a 32-bit signed or unsigned integer source value.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
FAQ
When does rm affect fcvt.d.wu?
A 32-bit integer to double-precision conversion is exact, so rm is encoded but does not change the numeric result.
What does the rs2 field select in fcvt.d.wu?
rs2 is not an ordinary source register; in the FCVT encoding it selects the WU unsigned 32-bit integer format.