When does rm matter for fcvt.d.wu?
It does not matter for the numeric result. The source integer is exactly representable in the destination floating-point format, so rm does not cause rounding.
FCVT.D.WU
RISC-V FCVT.D.WU Instruction Details
Instruction ManualR-typeConvert unsigned int32 to double: f[rd] = (double)(uint32_t)rs1. Always exact.
Instruction Syntax
fcvt.d.wu rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
DFloating-Point Convert
Instruction Behavior
fcvt.d.wu converts an unsigned 32-bit integer source to a double-precision floating-point result. This conversion is exact, so the encoded rounding mode does not change the numeric result.
Quick Understanding & Search Notes
fcvt.d.wu converts an unsigned 32-bit integer source to a double-precision floating-point result. This conversion is exact, so the encoded rounding mode does not change the numeric result.
The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.
This integer-to-floating-point conversion is exact; rm is encoded but does not change the numeric result.
W/WU forms read a 32-bit signed or unsigned integer source value.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
Common Usage Scenarios
Type Conversion
Understand this scenario with real code like «fcvt.d.wu f0, x10 # f0 = (double)(unsigned)x10».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
W/WU forms read a 32-bit signed or unsigned integer source value.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
FAQ
How does fcvt.d.wu differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.