Which registers does fcvt.s.wu use?
rd is FP; rs1 is integer, and rs2 only encodes the integer type.
FCVT.S.WU
RISC-V FCVT.S.WU Instruction Details
Instruction ManualOP-FPUnsigned Int32 to Single FP; round according to rm when inexact.
Instruction Syntax
fcvt.s.wu rd, rs1, rm
rd is FP f0–f31 (f0 is writable); rs1 is integer x0–x31; x0 always reads zero, and W/WU interpret the low 32 bits. rs2 selects the source type; no immediate.
32-bit OP-FP: funct5=11010, fmt=00 (destination S), rs2=00001, opcode=1010011.
RV32/RV64; requires F. Enable required extensions and FP state.
Optional rm defaults to dyn using frm; static 101/110 and dynamic frm=101–111 have reserved behavior. Inexact conversion rounds using rm and raises NX.
Integer sources need no boxing checks. S results set all upper bits to ones when FLEN>32. Exceptions accrue in fflags; flag setting alone causes no FP exception trap. Finite animation examples assume initial fflags=0.
FFloating-Point Convert
Instruction Behavior
fcvt.s.wu converts the low 32 bits of x[rs1], interpreted as an unsigned integer to single precision in FP rd. rm/frm selects rounding; inexact results set NX.
FCVT.S.WU Decode And Execute Animation
Shows the F-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the integer source, then write the floating-point destination.
rd
rs1
rm
fcvt.s.wu
,
,
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Execution Context
fmt=S (00)
rs2=WU
rounding: RNE nearest-even
fflags: NX
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11010
FCVT.S
00
fmt=S
00001
rs2=WU
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xD0158553
opcode
1010011 -> OP-FP
funct5/fmt
11010 + 00 -> FCVT.S.WU
rs2
00001 -> WU source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / a1(x11)
read
a1(x11) = 0xFFFFFFFF (4294967295)
convert
uint32 0xFFFFFFFF (4294967295) -> S 4294967296.0
write
fa0(f10) = 4294967296.0; NX
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
encoding: 0xD0158553
syntax : fcvt.s.wu fa0(f10), a1(x11), rne
result : fa0(f10) = 4294967296.0; NX
The current 32-bit integer example is not exactly representable as S format, so the rounded example shows NX.
FCVT Conversion View
WU source
0xFFFFFFFF (4294967295)
conversion
uint32 0xFFFFFFFF (4294967295) -> S 4294967296.0
writeback
fa0(f10) = 4294967296.0
The current 32-bit integer example is not exactly representable as S format, so the rounded example shows NX.
This animation shows only F-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
Unsigned Int32 to Single FP; round according to rm when inexact.
32-bit OP-FP: funct5=11010, fmt=00 (S), rs2=00001, opcode=1010011.
rd is f0–f31 and rs1 is x0–x31; W/WU interpret the signed/unsigned low 32 bits.
Integer sources need no NaN-boxing; narrower FP results set all upper FLEN bits to ones.
RV32/RV64; requires F. Enable required extensions and FP state.
Common Usage Scenarios
Integer to FP conversion
Understand this scenario with real code like «# x1 = 16777217; rm=rne; initial fflags=0 fcvt.s.wu f0, x1, rne # f0 = 16777216; fflags=NX».
Pre-Use Checklist
Syntax Check
- rd is FP f0–f31 (f0 is writable); rs1 is integer x0–x31; x0 always reads zero, and W/WU interpret the low 32 bits. rs2 selects the source type; no immediate.
- 32-bit OP-FP: funct5=11010, fmt=00 (destination S), rs2=00001, opcode=1010011.
Semantic Check
- RV32/RV64; requires F. Enable required extensions and FP state.
- Optional rm defaults to dyn using frm; static 101/110 and dynamic frm=101–111 have reserved behavior. Inexact conversion rounds using rm and raises NX.
- Integer sources need no boxing checks. S results set all upper bits to ones when FLEN>32. Exceptions accrue in fflags; flag setting alone causes no FP exception trap. Finite animation examples assume initial fflags=0.
Pitfalls / Common Confusions
rs2 selects the source type, not a second register operand.
Optional rm defaults to dyn using frm; static 101/110 and dynamic frm=101–111 have reserved behavior.
Input models the interpreted low 32 bits; x0 always reads zero.
S results set upper bits to ones when FLEN>32; inexact conversion raises NX.
FAQ
How does fcvt.s.wu use rm?
Inexact conversion rounds using rm and raises NX. Omitted rm defaults to dyn using frm; reserved encoding rules still apply.