Which register classes do rd and rs1 use in fcvt.s.w?
This is an integer-to-floating-point conversion: rs1 is an integer register and rd is a floating-point register.
FCVT.S.W
RISC-V FCVT.S.W Instruction Details
Instruction ManualR-typeConvert signed int32 to SP FP: f[rd] = (float)rs1.
Instruction Syntax
fcvt.s.w rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
FFloating-Point Convert
Instruction Behavior
fcvt.s.w converts a signed 32-bit integer source to a single-precision floating-point result. If the value is not exactly representable, the result is rounded according to rm and written to f[rd].
FCVT.S.W Decode And Execute Animation
Shows the F-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, rm rounding, read the integer source, then write the floating-point destination.
rd
rs1
rm
fcvt.s.w
,
,
Execution Context
fmt=S (00)
rs2=W
rounding: RNE nearest-even
fflags: 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11010
FCVT.S
00
fmt=S
00000
rs2=W
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xD0058553
opcode
1010011 -> OP-FP
funct5/fmt
11010 + 00 -> FCVT.S.W
rs2
00000 -> W source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / a1(x11)
read
a1(x11) = -42
convert
int32 -42 -> S -42.0
write
fa0(f10) = -42.0; 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT conversion instructions use opcode 1010011.
encoding: 0xD0058553
syntax : fcvt.s.w fa0(f10), a1(x11), rne
result : fa0(f10) = -42.0; 0
The current 32-bit integer example is exactly representable as S format, so example fflags remains 0.
FCVT Conversion View
W source
-42
conversion
int32 -42 -> S -42.0
writeback
fa0(f10) = -42.0
The current 32-bit integer example is exactly representable as S format, so example fflags remains 0.
This animation shows only F-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.s.w reads a signed 32-bit integer from integer register rs1, converts it to single precision, and writes f[rd]; if not exactly representable, it rounds according to rm and sets NX.
OP-FP opcode is 1010011; funct5=11010 denotes integer-to-FP FCVT and fmt=00 denotes S destination format.
rs2=00000 selects the W signed 32-bit integer source; rs1 is an integer register.
rd is an FP register, and the result is written in the destination format and NaN-boxed in wider FLEN.
rm controls rounding when the value is not exactly representable; exact conversion does not set NX.
The instruction does not read an FP source register, so there is no source NaN-boxing requirement.
Common Usage Scenarios
Register Operations
Understand this scenario with real code like «fcvt.s.w f0, x10, rne # f0 = (float)(int)x10».
Type Conversion
Understand this scenario with real code like «fcvt.s.w f0, x10, rne # f0 = (float)(int)x10».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
W/WU forms read a 32-bit signed or unsigned integer source value.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
FAQ
When does rm affect fcvt.s.w?
When the destination format cannot exactly represent the converted result, rm or DYN/frm selects the rounding direction; inexact conversion sets NX.
What does the rs2 field select in fcvt.s.w?
rs2 is not an ordinary source register; in the FCVT encoding it selects the W signed 32-bit integer format.