Does FMAX.D use the rm rounding mode?
No. The instruction uses funct3 to distinguish FMIN/FMAX and has no rm rounding operand in assembly syntax.
FMAX.D
RISC-V FMAX.D Instruction Details
Instruction ManualR-typeReturn the maximum of two double-precision floating-point operands.
Instruction Syntax
fmax.d rd, rs1, rs2
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
DFloating-Point Arithmetic
Instruction Behavior
FMAX.D selects the numerically larger double-precision operand. Ordinary FMIN/FMAX follows the official minimumNumber/maximumNumber rules: with exactly one NaN input it returns the non-NaN operand, with two NaNs it returns canonical NaN; signaling NaN sets NV, and -0.0 is less than +0.0.
FMAX.D Decode And Execute Animation
Shows the D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FMAX semantics, then write rd.
rd
rs1
rs2
fmax.d
,
,
Execution Context
FLEN>=64 / fmt=D (01)
funct3: FMAX selects maximum
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00101
FMAX
01
fmt=D
01100
rs2
01011
rs1
001
funct3=001
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x2AC59553
opcode
1010011 -> OP-FP
funct5/fmt
00101 + D(01) -> FMAX.D
funct3
001 -> FMAX selects maximum
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.
encoding: 0x2AC59553
syntax : fmax.d fa0(f10), fa1(f11), fa2(f12)
result : Not written yet; initial fflags=0
The default example shows the official signed-zero ordering: -0.0 is less than +0.0. With NaNs, ordinary FMIN/FMAX returns the non-NaN operand for a single NaN and canonical NaN for two NaNs; signaling NaN sets NV.
Double-precision Calculation
rs1
fa1(f11) = -0.0
rs2
fa2(f12) = 0.0
result
Awaiting Execute
The default example shows the official signed-zero ordering: -0.0 is less than +0.0. With NaNs, ordinary FMIN/FMAX returns the non-NaN operand for a single NaN and canonical NaN for two NaNs; signaling NaN sets NV.
Assumes required extensions and FS enabled, valid NaN-boxing, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros, infinities, qNaN, and sNaN are supported. Other inputs stop execution. One source register has one initial value; rd may overlap a source and f0 accepts writes. Steps are teaching views.
This animation shows only D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FMAX.D is a D-extension OP-FP selection instruction, not rounded arithmetic. The key points are how funct5/fmt/funct3 identify FMAX.D, and how NaNs and -0.0/+0.0 affect the selected result.
OP-FP opcode=1010011, funct5=00101, fmt=D, and funct3=001 identify FMAX.D.
Ordinary FMIN/FMAX returns the non-NaN operand for a single NaN; two NaNs return canonical NaN, and signaling NaN sets NV.
-0.0 is less than +0.0; the default animation example is chosen to show this official ordering rule.
There is no rm rounding operand, so the animation shows ISA-visible selection and writeback rather than a rounding path.
The animation accepts exact whitelist values, signed zeros, qnan, snan, and infinities; initial fflags=0. Invalid NaN-boxing is not simulated.
When FLEN>64, D sources must be NaN-boxed or are read as canonical D NaNs; upper result bits are written as all ones.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — 21.2–21.6: rounding, flags, FMA and FMIN/FMAXThe RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — 22.2: NaN-boxingThe RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — 22.4: D computational instructionsThe RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — 26.2: FMAXM NaN behavior
Common Usage Scenarios
Floating-Point Compare
Understand this scenario with real code like «fmax.d f0, f1, f2 # f1=-0.0, f2=+0.0 -> f0=+0.0».
Numerical Computing
Understand this scenario with real code like «fmax.d f0, f1, f2 # f1=-0.0, f2=+0.0 -> f0=+0.0».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register receiving the formatted result.
- rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
- Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
- Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.
Pitfalls / Common Confusions
Ordinary FMIN/FMAX returns the non-NaN operand when exactly one input is NaN; do not confuse it with Zfa FMINM/FMAXM.
A signaling NaN sets NV; when both inputs are NaNs, the result is canonical NaN.
-0.0 is less than +0.0 by the official rule, so signed zero can change the selected result.
This instruction has no rm rounding operand; funct3 selects FMIN or FMAX.
FAQ
How does FMAX.D differ from FMAXM.D?
The ordinary form returns the other non-NaN operand when exactly one input is NaN; the Zfa M form returns canonical NaN if either input is NaN.