What does FMAX.Q do with one NaN operand?
Ordinary FMIN/FMAX returns the other non-NaN operand when exactly one operand is NaN; it returns canonical NaN when both operands are NaN.
FMAX.Q
RISC-V FMAX.Q Instruction Details
Instruction ManualR-typeFMAX.Q selects the numerically larger value from two quad-precision floating-point operands.
Instruction Syntax
fmax.q rd, rs1, rs2
Operand Breakdown
rd, rs1, rs2: FP registers f0–f31 or their ABI names; f0 is writable and rd may overlap a source.
No rm, rs3, or immediate operand; funct3=001 selects ordinary FMAX and funct3=011 selects Zfa FMAXM.
QFloating-Point Arithmetic
Instruction Behavior
FMAX.Q uses the OP-FP encoding with the Q format to select the numerically larger value from two quad-precision source operands. Ordinary FMIN/FMAX returns the non-NaN operand when exactly one input is NaN, returns canonical NaN when both inputs are NaN, and sets NV if either input is a signaling NaN. The official rule orders -0.0 below +0.0.
FMAX.Q Decode And Execute Animation
Shows the Q-extension quad-precision OP-FP flow: decode fields, read FP operands, perform FMAX semantics, then write rd.
rd
rs1
rs2
fmax.q
,
,
Execution Context
FLEN=128 / fmt=Q (11)
funct3: FMAX selects maximum
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00101
FMAX
11
fmt=Q
01100
rs2
01011
rs1
001
funct3=001
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x2EC59553
opcode
1010011 -> OP-FP
funct5/fmt
00101 + Q(11) -> FMAX.Q
funct3
001 -> FMAX selects maximum
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; quad-precision OP-FP instructions use opcode 1010011.
encoding: 0x2EC59553
syntax : fmax.q fa0(f10), fa1(f11), fa2(f12)
result : Not written yet; initial fflags=0
The default example shows the official signed-zero ordering: -0.0 is less than +0.0. With NaNs, ordinary FMIN/FMAX returns the non-NaN operand for a single NaN and canonical NaN for two NaNs; signaling NaN sets NV.
Quad-precision Calculation
rs1
fa1(f11) = -0.0
rs2
fa2(f12) = 0.0
result
Awaiting Execute
The default example shows the official signed-zero ordering: -0.0 is less than +0.0. With NaNs, ordinary FMIN/FMAX returns the non-NaN operand for a single NaN and canonical NaN for two NaNs; signaling NaN sets NV.
Assumes required extensions and FS enabled, valid NaN-boxing, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros, infinities, qNaN, and sNaN are supported. Other inputs stop execution. One source register has one initial value; rd may overlap a source and f0 accepts writes. Steps are teaching views.
This animation shows only Q-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FMAX.Q selects a quad-precision maximum into an FP destination register; one NaN returns the non-NaN operand, and two NaNs return canonical NaN.
Applies to RV32/RV64 Q 2.2 (requires D and F); FP state must be enabled. Its 128-bit precision is distinct from XLEN.
32-bit R-type OP-FP: funct5[31:27]=00101, fmt[26:25]=11, rs2[24:20], rs1[19:15], funct3[14:12]=001, rd[11:7], opcode[6:0]=1010011; no rm, rs3, or immediate.
rd, rs1, and rs2 select f0–f31 or their ABI names; f0 accepts writes and rd may overlap a source. Sources narrower than FLEN require valid NaN-boxing or are treated as canonical NaN of that format; narrow results have all-one upper bits.
One NaN returns the non-NaN operand and two NaNs return canonical NaN; only sNaN sets NV. qNaN does not set NV or clear old flags. fflags accrues exceptions; flag setting alone causes no base FP exception trap.
For these selection operations only, -0.0 is considered below +0.0, so -0/+0 selects +0. The animation starts with fflags=0 and accepts exact whitelisted finite inputs plus signed zeros, infinities, qNaN, and sNaN; steps are teaching views.
Common Usage Scenarios
Floating-Point Compare
Assume required extensions and FP state enabled, f1=-0.0 and f2=+0.0 in this instruction's format (validly NaN-boxed for wider FLEN), and initial fflags=0: the example writes f0=+0.0 with fflags still 0. f0 is writable.
Numerical Computing
Assume required extensions and FP state enabled, f1=-0.0 and f2=+0.0 in this instruction's format (validly NaN-boxed for wider FLEN), and initial fflags=0: the example writes f0=+0.0 with fflags still 0. f0 is writable.
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: FP registers f0–f31 or their ABI names; f0 is writable and rd may overlap a source.
- No rm, rs3, or immediate operand; funct3=001 selects ordinary FMAX and funct3=011 selects Zfa FMAXM.
Semantic Check
- Confirm required extensions and FP state are enabled, source formats match, and inputs in wider FLEN are correctly NaN-boxed.
- Select by this page's NaN and signed-zero rules; only sNaN sets NV, existing fflags are not cleared, and rm is unused.
Pitfalls / Common Confusions
Ordinary FMIN/FMAX returns the non-NaN operand when exactly one input is NaN; do not treat it as always propagating NaN.
A signaling NaN sets NV; quiet NaN and signaling NaN differ in exception-flag behavior.
-0.0 is ordered below +0.0 by the official rule, which affects the sign of FMIN/FMAX results.
FMIN/FMAX has no rm rounding field and is not rounded add/subtract/multiply/divide arithmetic.
FAQ
Does FMAX.Q use rm rounding?
No. FMIN/FMAX is a selection operation; its funct3 selects minimum or maximum semantics, not a rounding mode.