What is the main difference from the ordinary form?
The M form returns canonical NaN if either input is NaN; the ordinary form returns the other non-NaN operand when exactly one input is NaN.
FMAXM.H
RISC-V FMAXM.H Instruction Details
Instruction ManualR-typeReturn the maximum of two half-precision floating-point operands.
Instruction Syntax
fmaxm.h rd, rs1, rs2
Operand Breakdown
rd, rs1, rs2: FP registers f0–f31 or their ABI names; f0 is writable and rd may overlap a source.
No rm, rs3, or immediate operand; funct3=001 selects ordinary FMAX and funct3=011 selects Zfa FMAXM.
ZfaZfhFloating-Point Arithmetic
Instruction Behavior
FMAXM.H is the Zfa half-precision IEEE 754-2019 maximum operation: if either input is NaN, the result is canonical NaN; otherwise it returns the numerically larger operand and handles -0.0 versus +0.0 as specified.
FMAXM.H Decode And Execute Animation
Shows the Zfa + Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FMAXM semantics, then write rd.
rd
rs1
rs2
fmaxm.h
,
,
Execution Context
FLEN>=32 / fmt=H (10)
funct3: FMAXM (either NaN is canonical NaN)
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00101
FMAXM
10
fmt=H
01100
rs2
01011
rs1
011
funct3=011
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x2CC5B553
opcode
1010011 -> OP-FP
funct5/fmt
00101 + H(10) -> FMAXM.H
funct3
011 -> FMAXM (either NaN is canonical NaN)
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.
encoding: 0x2CC5B553
syntax : fmaxm.h fa0(f10), fa1(f11), fa2(f12)
result : Not written yet; initial fflags=0
The default example shows the official signed-zero ordering: -0.0 is less than +0.0. If either input is NaN, Zfa FMINM/FMAXM returns canonical NaN; a signaling NaN sets NV.
Half-precision Calculation
rs1
fa1(f11) = -0.0
rs2
fa2(f12) = 0.0
result
Awaiting Execute
The default example shows the official signed-zero ordering: -0.0 is less than +0.0. If either input is NaN, Zfa FMINM/FMAXM returns canonical NaN; a signaling NaN sets NV.
Assumes required extensions and FS enabled, valid NaN-boxing, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros, infinities, qNaN, and sNaN are supported. Other inputs stop execution. One source register has one initial value; rd may overlap a source and f0 accepts writes. Steps are teaching views.
This animation shows only Zfa + Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FMAXM.H selects a half-precision maximum into an FP destination register; either NaN produces canonical NaN.
Applies to RV32/RV64 Zfa 1.0 + full Zfh 1.0 (requires F, not Zfhmin); FP state must be enabled. Its 16-bit precision is distinct from XLEN.
32-bit R-type OP-FP: funct5[31:27]=00101, fmt[26:25]=10, rs2[24:20], rs1[19:15], funct3[14:12]=011, rd[11:7], opcode[6:0]=1010011; no rm, rs3, or immediate.
rd, rs1, and rs2 select f0–f31 or their ABI names; f0 accepts writes and rd may overlap a source. Sources narrower than FLEN require valid NaN-boxing or are treated as canonical NaN of that format; narrow results have all-one upper bits.
Either NaN returns canonical NaN; only sNaN sets NV. qNaN does not set NV or clear old flags. fflags accrues exceptions; flag setting alone causes no base FP exception trap.
For these selection operations only, -0.0 is considered below +0.0, so -0/+0 selects +0. The animation starts with fflags=0 and accepts exact whitelisted finite inputs plus signed zeros, infinities, qNaN, and sNaN; steps are teaching views.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 21The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 24The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 26
Common Usage Scenarios
Floating-Point Compare
Assume required extensions and FP state enabled, f1=-0.0 and f2=+0.0 in this instruction's format (validly NaN-boxed for wider FLEN), and initial fflags=0: the example writes f0=+0.0 with fflags still 0. f0 is writable.
Numerical Computing
Assume required extensions and FP state enabled, f1=-0.0 and f2=+0.0 in this instruction's format (validly NaN-boxed for wider FLEN), and initial fflags=0: the example writes f0=+0.0 with fflags still 0. f0 is writable.
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: FP registers f0–f31 or their ABI names; f0 is writable and rd may overlap a source.
- No rm, rs3, or immediate operand; funct3=001 selects ordinary FMAX and funct3=011 selects Zfa FMAXM.
Semantic Check
- Confirm required extensions and FP state are enabled, source formats match, and inputs in wider FLEN are correctly NaN-boxed.
- Select by this page's NaN and signed-zero rules; only sNaN sets NV, existing fflags are not cleared, and rm is unused.
Pitfalls / Common Confusions
Unlike ordinary FMIN/FMAX, FMINM/FMAXM returns canonical NaN if either input is NaN.
sNaN sets NV; qNaN returns canonical NaN without setting NV, and existing fflags are not cleared.
-0.0 is considered less than +0.0.
FAQ
Does FMAXM.H round?
No. It selects between two operands and has no rm rounding field.