How is FMSUB.H different from FMUL plus add/subtract?
FMSUB.H is fused: the product is not first rounded into an intermediate FP result; the whole expression is rounded once at the end according to rm.
FMSUB.H
RISC-V FMSUB.H Instruction Details
Instruction ManualR4-typehalf-precision fused multiply-subtract: rd = (rs1 * rs2) - rs3, with one final rounding according to rm.
Instruction Syntax
fmsub.h rd, rs1, rs2, rs3, rm
Operand Breakdown
rd: destination floating-point register.
rs1, rs2, rs3: three source floating-point registers; R4 is not an ordinary three-register R-type form.
rm: rounding-mode field for the final fused multiply-add/subtract result.
ZfhFloating-Point Arithmetic
Instruction Behavior
FMSUB.H uses the R4 four-register format for half-precision fused multiply-subtract. The rs1*rs2 product is not rounded or written as an intermediate result; it is combined with rs3 as one fused expression, rounded once according to rm, and written to rd.
FMSUB.H Decode And Execute Animation
Shows the Zfh-extension half-precision R4 fused multiply-add flow: decode fields, read FP operands, perform FMSUB semantics, then write rd.
rd
rs1
rs2
rs3
rm
fmsub.h
,
,
,
,
Execution Context
FLEN=>=32 / fmt=H (10)
rounding: RNE nearest-even
fflags: example fflags remains 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01101
rs3
10
fmt=H
01100
rs2
01011
rs1
000
rm
01010
rd
1000111
MSUB
Execution Data Path
instruction
0x6CC58547
opcode
1000111 -> MSUB
rs3/fmt
fa3(f13) + H(10) -> R4 FMSUB
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12) / fa3(f13)
read
1.5, 2.0, 1.0
fused op
(1.5 * 2.0) - 1.0 = 2.0
write
fa0(f10) = 2.0; example fflags remains 0
Current Step
Fetch: show the 32-bit R4 encoding
The word is split as an R4-type instruction; FMSUB.H uses its dedicated major opcode 1000111, not the ordinary OP-FP opcode.
encoding: 0x6CC58547
syntax : fmsub.h fa0(f10), fa1(f11), fa2(f12), fa3(f13), rne
result : fa0(f10) = 2.0; example fflags remains 0
The default example (1.5 * 2.0) - 1.0 = 2.0 is exactly checkable; the fused operation rounds once at the end, so example fflags remains 0.
Half-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 2.0
rs3
fa3(f13) = 1.0
result
(1.5 * 2.0) - 1.0 = 2.0
The default example (1.5 * 2.0) - 1.0 = 2.0 is exactly checkable; the fused operation rounds once at the end, so example fflags remains 0.
This animation shows only Zfh-extension ISA-visible R4 encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FMSUB.H's key points are R4 encoding and fused semantics: rs3 is a real third source register, and the product plus/minus term forms one exact intermediate expression that is rounded only once.
R4 major opcode=1000111 identifies the MSUB fused operation class, and fmt=H selects the half-precision format.
The encoded field order is rs3 | fmt | rs2 | rs1 | rm | rd | opcode; this differs from ordinary OP-FP R-type instructions.
The semantic expression is rd = (rs1 * rs2) - rs3, and the fused operation is rounded once at the end according to rm/frm.
The animation default uses exactly checkable finite values; NaN, infinity, overflow, underflow, and inexact paths are covered by the official static explanation.
Common Usage Scenarios
Fused Floating Point
Understand this scenario with real code like «fmsub.h f0, f1, f2, f3, rne # f0 = (rs1 * rs2) - rs3».
Numerical Computing
Understand this scenario with real code like «fmsub.h f0, f1, f2, f3, rne # f0 = (rs1 * rs2) - rs3».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register.
- rs1, rs2, rs3: three source floating-point registers; R4 is not an ordinary three-register R-type form.
- rm: rounding-mode field for the final fused multiply-add/subtract result.
Semantic Check
- Confirm rs3 participates in the fused operation and the result is rounded only once at the end.
- Confirm the sign rules for FNMADD/FNMSUB match the intended operation.
Pitfalls / Common Confusions
FMSUB.H is a fused operation, not the same as FMUL followed by FADD/FSUB with two roundings.
In the R4 encoding, bits 31..27 are the rs3 field; do not decode them as an ordinary OP-FP R-type funct5 field.
rm controls the single final rounding; inexact, overflow, underflow, invalid-operation, and special-value paths are recorded by the official FP exception-flag rules.
The FNMSUB/FNMADD sign rules are easy to confuse: FNMSUB is -(rs1*rs2)+rs3, while FNMADD is -(rs1*rs2)-rs3.
FAQ
Why is FMSUB.H R4-type?
It needs rd, rs1, rs2, rs3, and rm fields; bits 31..27 hold rs3, not an ordinary R-type funct5 field.
Can FMSUB.H set fflags?
It can set FP exception flags under the official FP rules, such as inexact, overflow, underflow, or invalid operation; the default animation uses exact finite values, so it shows fflags remaining 0.