Does it use integer or floating-point registers?
rd, rs1, and rs2 are floating-point register fields. Integer registers interact with FP data through conversion, move, or load/store instructions.
FMUL.S
RISC-V FMUL.S Instruction Details
Instruction ManualR-typePerforms single-precision floating-point multiplication: rd = rs1 * rs2, rounded by the rm field or dynamic frm.
Instruction Syntax
fmul.s rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
FFloating-Point Arithmetic
Instruction Behavior
FMUL.S multiplies single-precision values in rs1 and rs2; result to rd. R-type. Rounding by rm. Subnormals are supported, and applicable IEEE 754 floating-point exception flags are accrued.
FMUL.S Decode And Execute Animation
Shows the F-extension single-precision OP-FP flow: decode fields, read FP operands, perform FMUL semantics, then write rd.
rd
rs1
rs2
rm
fmul.s
,
,
,
Execution Context
FLEN=32 / fmt=S (00)
rounding: RNE nearest-even
fflags: example fflags remains 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00010
FMUL
00
fmt=S
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x10C58553
opcode
1010011 -> OP-FP
funct5/fmt
00010 + S(00) -> FMUL.S
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
3.5, 2.0
FP op
3.5 * 2.0 = 7.0
write
fa0(f10) = 7.0; example fflags remains 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; single-precision OP-FP instructions use opcode 1010011.
encoding: 0x10C58553
syntax : fmul.s fa0(f10), fa1(f11), fa2(f12), rne
result : fa0(f10) = 7.0; example fflags remains 0
The animation displays a teaching result from editable example values; final rounding and fflags follow the official RISC-V F rules.
Single-precision Calculation
rs1
fa1(f11) = 3.5
rs2
fa2(f12) = 2.0
result
3.5 * 2.0 = 7.0
The animation displays a teaching result from editable example values; final rounding and fflags follow the official RISC-V F rules.
This animation shows only F-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FMUL.S is an OP-FP arithmetic instruction from the RISC-V F extension. It reads two single-precision FP registers, rounds the product by rm/frm, and writes the result to FP register rd.
The .S suffix denotes the 32-bit single-precision floating-point format, using the F-extension OP-FP encoding.
The rm field selects a static rounding mode; rm=111 uses the dynamic frm rounding mode.
The product may overflow, underflow, or be inexact; these conditions are recorded through the fflags floating-point exception flags.
Common Usage Scenarios
Floating-point arithmetic
Understand this scenario with real code like «fmul.s f0, f1, f2 # f0 = f1*f2 (RNE)».
Numerical computing
Understand this scenario with real code like «fmul.s f0, f1, f2 # f0 = f1*f2 (RNE)».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register receiving the formatted result.
- rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
- Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
- Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.
Pitfalls / Common Confusions
rd, rs1, and rs2 are floating-point registers, not integer x registers.
The product may overflow, underflow, or be inexact; result and fflags follow FP rules and rounding mode.
FMUL.S is not fused multiply-add; use FMADD.S and related R4 instructions for fused multiply-add semantics.
FAQ
How does rm affect the result?
rm selects the rounding mode, or uses frm for the dyn encoding. For inexact results, the rounding mode affects the written value and may set fflags.
Do floating-point exceptions trap like integer exceptions?
The F extension records floating-point exception flags in fflags; this page does not describe them as integer condition codes or integer overflow traps.