Does it use integer or floating-point registers?
rd, rs1, and rs2 select FP registers f0–f31. f0 is an ordinary FP register; its writeback is not discarded like integer x0.
FADD.S
RISC-V FADD.S Instruction Details
Instruction ManualR-typePerforms single-precision floating-point addition: rd = rs1 + rs2, rounded by the rm field or dynamic frm.
Instruction Syntax
fadd.s rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
FFloating-Point Arithmetic
Instruction Behavior
FADD.S adds the single-precision values in rs1 and rs2 and writes the result to rd. This R-type instruction uses the OP-FP opcode with fmt=S(00); rm selects static rounding and rm=111 uses frm. Its applicable exception flags are NV, OF, and NX, accrued in fflags. Subnormals follow IEEE 754-2008 rules; when FLEN is greater than 32, inputs must be valid NaN-boxed single-precision values or are treated as canonical NaN.
FADD.S Decode And Execute Animation
Shows the F-extension single-precision OP-FP flow: decode fields, read FP operands, perform FADD semantics, then write rd.
rd
rs1
rs2
rm
fadd.s
,
,
,
Execution Context
FLEN=>=32 / fmt=S (00)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00000
FADD
00
fmt=S
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x00C58553
opcode
1010011 -> OP-FP
funct5/fmt
00000 + S(00) -> FADD.S
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; single-precision OP-FP instructions use opcode 1010011.
encoding: 0x00C58553
syntax : fadd.s fa0(f10), fa1(f11), fa2(f12), rne
result : Not written yet; initial fflags=0
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
Single-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 2.25
result
Awaiting Execute
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only F-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FADD.S is an OP-FP arithmetic instruction from the RISC-V F extension. It reads two single-precision FP registers, rounds by rm/frm, writes the result to FP register rd, and records FP exceptions in fflags.
The .S suffix denotes the 32-bit single-precision floating-point format, using the F-extension OP-FP encoding.
The rm field selects a static rounding mode; rm=111 uses the dynamic frm rounding mode.
FADD.S has applicable exception flags NV, OF, and NX; it does not produce UF or DZ. When FLEN is greater than 32, an incorrectly NaN-boxed input is treated as canonical NaN.
Available on RV32 and RV64; F depends on Zicsr. In a privileged environment, FS=Off makes accesses to FP state raise an illegal-instruction exception.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (20260120), F Extension 2.2RISC-V Assembly Programmer’s Manual (v0.0.0, 2025-02-05; release v0.0.1), Floating-point rounding modesThe RISC-V Instruction Set Manual, Volume II: Privileged Architecture (20260120), Extension Context Status
Common Usage Scenarios
Floating-point arithmetic
Understand this scenario with real code like «fadd.s f0, f1, f2, rne # f0 = f1 + f2».
Numerical computing
Understand this scenario with real code like «fadd.s f0, f1, f2, rne # f0 = f1 + f2».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register receiving the formatted result.
- rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
- Confirm 32-bit S format and FP inputs match, with valid NaN-boxing in wider FLEN.
- Inspect accrued fflags for NV, OF, NX when needed; setting FP exception flags does not itself trap.
Pitfalls / Common Confusions
rd, rs1, and rs2 are floating-point registers, not integer x registers.
The rm field or dynamic frm selects rounding; do not treat one exact example as a proof for every rounding mode.
FADD.S can accrue only NV, OF, and NX, not UF or DZ. When FLEN is greater than 32, an incorrectly NaN-boxed input is treated as canonical NaN.
FAQ
How does rm affect the result?
rm selects the rounding mode, or uses frm for the dyn encoding. For inexact results, the rounding mode affects the written value and may set fflags.
Do floating-point exceptions trap like integer exceptions?
The base ISA does not generate a trap when an FP exception flag is set; software explicitly inspects fflags. An illegal instruction caused by disabled FP state is a separate case.
Can rm be omitted?
Omitting rm in assembly defaults to dyn and uses frm; explicit rne selects static nearest-even rounding. Behavior for static rm=101/110 or dynamic frm=101/110/111 is reserved; a trap is not universally required.
What are the fflags and animation assumptions?
FP exception flags accrue in fflags; the base ISA does not trap on setting them. The animation assumes the extension is available, FP state is enabled, inputs are correctly NaN-boxed, and initial fflags=0. It accepts only nonzero finite exact whitelisted inputs and nonzero whitelisted results, excluding zero, NaN, infinity, overflow, underflow, and inexact paths. With wider FLEN, result upper bits are all 1s for valid NaN-boxing.