Performs double-precision floating-point addition: rd = rs1 + rs2, rounded by the rm field or dynamic frm.
FADD.D adds the double-precision floating-point values in rs1 and rs2 and writes the result to rd. This R-type OP-FP instruction uses fmt=D(01); rounding is selected by rm or by frm when rm is DYN, and its applicable exception flags are NV, OF, and NX, accrued in fflags. If FLEN is greater than 64, narrower double-precision values are checked using NaN-boxing, and inputs whose upper bits are not all 1s are treated as canonical NaN.
Shows the D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FADD semantics, then write rd.
The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
FADD.D is D-extension double-precision addition: register fields select FP registers, fmt=01 selects D format, rm/frm selects rounding, and the result is written to FP rd while fflags accrue under the official floating-point rules.
Understand this scenario with real code like «fadd.d fa0, fa1, fa2, rne # fa0 = fa1 + fa2».
Understand this scenario with real code like «fadd.d fa0, fa1, fa2, rne # fa0 = fa1 + fa2».
FADD.D uses the D-extension double-precision format with fmt=01 and operates on 64-bit floating-point values; FADD.S uses the F-extension single-precision format with fmt=00 and operates on 32-bit values.
When the sum is not exactly representable in the target double-precision format or overflows, rm or dynamic frm selects rounding; the applicable flags are NX, OF, and NV.
No. rd, rs1, and rs2 are floating-point register fields; the result is written to FP rd, not to an integer x register.
Omitting rm in assembly defaults to dyn and uses frm; explicit rne selects static nearest-even rounding. Behavior for static rm=101/110 or dynamic frm=101/110/111 is reserved; a trap is not universally required.
FP exception flags accrue in fflags; the base ISA does not trap on setting them. The animation assumes the extension is available, FP state is enabled, inputs are correctly NaN-boxed, and initial fflags=0. It accepts only nonzero finite exact whitelisted inputs and nonzero whitelisted results, excluding zero, NaN, infinity, overflow, underflow, and inexact paths. With wider FLEN, result upper bits are all 1s for valid NaN-boxing.