FADD.D
RISC-V FADD.D Instruction Details
Instruction ManualR-typeDouble-precision floating-point addition: rd = rs1+rs2.
Instruction Syntax
fadd.d rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
DFloating-Point Arithmetic
Instruction Behavior
FADD.D performs double-precision floating-point addition: rd = rs1 + rs2. R-type, fmt=D(01). Rounding mode by rm field. Inputs checked for proper NaN-boxing: if FLEN>64 (e.g., Q present), upper FLEN-64 bits must be all 1s, else treated as canonical NaN. The result follows IEEE 754-2008 and accrues the floating-point exception flags applicable to this operation. NaN result is canonical NaN (0x7ff8000000000000).
Common Usage Scenarios
Basic Arithmetic
Understand this scenario with real code like «fadd.d f0, f1, f2 # f0 = f1+f2 (RNE)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
inputs must be properly NaN-boxed (upper bits all 1s when FLEN>64), else treated as canonical NaN
rounding mode affects exception flags and final result
subnormals per IEEE 754-2008; tininess detected after rounding