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FADD.D

RISC-V FADD.D Instruction Details

Instruction ManualR-type

Performs double-precision floating-point addition: rd = rs1 + rs2, rounded by the rm field or dynamic frm.

Instruction Syntax

fadd.d rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
DFloating-Point Arithmetic
Related Search Terms
FADD.D instructionRISC-V FADD.Dfadd.d syntaxfadd.d encodingfadd.d rmdouble precision addRISC-V D extensionOP-FP encoding

Instruction Behavior

FADD.D adds the double-precision floating-point values in rs1 and rs2 and writes the result to rd. This R-type OP-FP instruction uses fmt=D(01); rounding is selected by rm or by frm when rm is DYN, and applicable floating-point exception flags accrue in fflags. If FLEN is greater than 64, narrower double-precision values are checked using NaN-boxing, and inputs whose upper bits are not all 1s are treated as canonical NaN.

FADD.D Decode And Execute Animation

Shows the D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FADD semantics, then write rd.

rd
rs1
rs2
rm
fadd.d
,
,
,
Execution Context
FLEN=64 / fmt=D (01)
rounding: RNE nearest-even
fflags: example fflags remains 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00000
FADD
01
fmt=D
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x02C58553
opcode
1010011 -> OP-FP
funct5/fmt
00000 + D(01) -> FADD.D
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
1.5, 2.25
FP op
1.5 + 2.25 = 3.75
write
fa0(f10) = 3.75; example fflags remains 0
Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.

encoding: 0x02C58553
syntax : fadd.d fa0(f10), fa1(f11), fa2(f12), rne
result : fa0(f10) = 3.75; example fflags remains 0

The animation displays a teaching result from editable example values; final rounding and fflags follow the official RISC-V D rules.

Double-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 2.25
result
1.5 + 2.25 = 3.75

The animation displays a teaching result from editable example values; final rounding and fflags follow the official RISC-V D rules.

This animation shows only D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FADD.D is D-extension double-precision addition: register fields select FP registers, fmt=01 selects D format, rm/frm selects rounding, and the result is written to FP rd while fflags accrue under the official floating-point rules.

The OP-FP opcode is 1010011; funct5 selects FADD/FSUB/FMUL, and fmt=01 selects the D double-precision format.
The rm field selects a static rounding mode; rm=111 uses the dynamic rounding mode from fcsr.frm.
Floating-point exception flags are accrued, and the operation may set applicable NV, OF, UF, NX, and related flags.
NaN results use the canonical NaN; when FLEN is greater than 64, double-precision values must satisfy NaN-boxing.
RISC-V Unprivileged ISA Manual: D double-precision floating-point extensionRISC-V Unprivileged ISA Manual: F extension rounding modes and fflags

Common Usage Scenarios

Double-precision numerical computing

Understand this scenario with real code like «fadd.d fa0, fa1, fa2, rne # fa0 = fa1 + fa2».

Floating-point arithmetic

Understand this scenario with real code like «fadd.d fa0, fa1, fa2, rne # fa0 = fa1 + fa2».

Pre-Use Checklist

Syntax Check
  • rd: destination floating-point register receiving the formatted result.
  • rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
  • Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
  • Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.

Pitfalls / Common Confusions

rm=111 means the dynamic rounding mode from frm; other reserved rm encodings should not be used as legal examples.
Inexact, overflow, underflow, invalid-operation, and related cases accrue in fflags; the exact example result does not represent every input.
If implemented FLEN is greater than 64, double-precision inputs must be properly NaN-boxed; otherwise they are treated as canonical NaN.

FAQ

What is the main difference between FADD.D and FADD.S?

FADD.D uses the D-extension double-precision format with fmt=01 and operates on 64-bit floating-point values; FADD.S uses the F-extension single-precision format with fmt=00 and operates on 32-bit values.

When does the rm field affect FADD.D?

When the addition result is not exactly representable in the target double-precision format, or when overflow, underflow, or similar boundary cases occur, rm or dynamic frm selects the rounding direction and may affect fflags.

Does FADD.D modify integer registers?

No. rd, rs1, and rs2 are floating-point register fields; the result is written to FP rd, not to an integer x register.