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FSUB.D

RISC-V FSUB.D Instruction Details

Instruction ManualR-type

Performs double-precision floating-point subtraction: rd = rs1 - rs2, rounded by the rm field or dynamic frm.

Instruction Syntax

fsub.d rd, rs1, rs2, rm

Operand Breakdown

rd: destination floating-point register receiving the formatted result.

rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.

DFloating-Point Arithmetic

Related Search Terms

FSUB.D instruction RISC-V FSUB.D fsub.d syntax fsub.d encoding fsub.d rm double precision subtract RISC-V D extension OP-FP encoding

Instruction Behavior

FSUB.D subtracts the double-precision floating-point value in rs2 from rs1 and writes the result to rd. This R-type OP-FP instruction uses fmt=D(01), with rs2 as the subtrahend; rounding is selected by rm or by frm when rm is DYN, and its applicable exception flags are NV, OF, and NX, accrued in fflags. If FLEN is greater than 64, double-precision inputs are checked using NaN-boxing and inputs whose upper bits are not all 1s are treated as canonical NaN.

FSUB.D Decode And Execute Animation

Shows the D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FSUB semantics, then write rd.

rs1

rs2

fsub.d

Execution Context

FLEN=>=64 / fmt=D (01)

rounding: RNE nearest-even

fflags: example fflags remains 0

fa1(f11) valueThe animation accepts only whitelisted finite exact examples; NaN/inf and rounding boundaries are covered in static textfa2(f12) valueThe animation accepts only whitelisted finite exact examples; NaN/inf and rounding boundaries are covered in static text

31..27

26..25

24..20

19..15

14..12

11..7

6..0

00001

FSUB

fmt=D

01100

rs2

01011

rs1

000

01010

1010011

OP-FP

Execution Data Path

instruction

0x0AC58553

opcode

1010011 -> OP-FP

funct5/fmt

00001 + D(01) -> FSUB.D

000 -> RNE nearest-even

rd/rs

fa0(f10) / fa1(f11) / fa2(f12)

read

7.5, 2.25

FP op

7.5 - 2.25 = 5.25

write

fa0(f10) = 5.25; example fflags remains 0

Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.

encoding: 0x0AC58553

syntax : fsub.d fa0(f10), fa1(f11), fa2(f12), rne

result : fa0(f10) = 5.25; example fflags remains 0

This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.

Double-precision Calculation

rs1

fa1(f11) = 7.5

rs2

fa2(f12) = 2.25

result

7.5 - 2.25 = 5.25

This animation shows only D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FSUB.D is D-extension double-precision subtraction: the semantic order is rs1 - rs2, not rs2 - rs1; fmt=01 selects D format, and rm/frm controls rounding and may affect fflags.

The OP-FP opcode is 1010011; funct5 selects FADD/FSUB/FMUL, and fmt=01 selects the D double-precision format.

The rm field selects a static rounding mode; rm=111 uses the dynamic rounding mode from fcsr.frm.

FSUB.D has applicable exception flags NV, OF, and NX; it does not produce UF or DZ, and the flags accrue in fflags.

NaN results use the canonical NaN; when FLEN is greater than 64, double-precision values must satisfy NaN-boxing.

RISC-V Unprivileged ISA Manual: D double-precision floating-point extension RISC-V Unprivileged ISA Manual: F extension rounding modes and fflags

Common Usage Scenarios

Double-precision numerical computing

Understand this scenario with real code like «fsub.d fa0, fa1, fa2, rne # fa0 = fa1 - fa2».

Floating-point arithmetic

Understand this scenario with real code like «fsub.d fa0, fa1, fa2, rne # fa0 = fa1 - fa2».

Pre-Use Checklist

Syntax Check

rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.

Semantic Check

Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.

Pitfalls / Common Confusions

rm=111 means the dynamic rounding mode from frm; other reserved rm encodings should not be used as legal examples.

FSUB.D can accrue only NV, OF, and NX, not UF or DZ; the exact example result does not represent every input.

If implemented FLEN is greater than 64, double-precision inputs must be properly NaN-boxed; otherwise they are treated as canonical NaN.

FAQ

What is the main difference between FSUB.D and FSUB.S?

FSUB.D uses the D-extension double-precision format with fmt=01 and operates on 64-bit floating-point values; FSUB.S uses the F-extension single-precision format with fmt=00 and operates on 32-bit values.

When does the rm field affect FSUB.D?

When the difference is not exactly representable in the target double-precision format or overflows, rm or dynamic frm selects rounding; the applicable flags are NX, OF, and NV.

Does FSUB.D modify integer registers?

No. rd, rs1, and rs2 are floating-point register fields; the result is written to FP rd, not to an integer x register.