Does it use integer or floating-point registers?
rd, rs1, and rs2 are floating-point register fields. Integer registers interact with FP data through conversion, move, or load/store instructions.
FSUB.S
RISC-V FSUB.S Instruction Details
Instruction ManualR-typePerforms single-precision floating-point subtraction: rd = rs1 - rs2; rm=111 selects dynamic frm, while reserved rm encodings have reserved behavior.
Instruction Syntax
fsub.s rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
FFloating-Point Arithmetic
Instruction Behavior
FSUB.S is an F-extension OP-FP R-type instruction: it subtracts the single-precision value in rs2 from rs1 and writes FP register rd. fmt=00 selects single precision; rm selects static rounding and rm=111 uses frm. Static rm=101--110 and reserved dynamic-frm encodings have reserved behavior.
FSUB.S Decode And Execute Animation
Shows the F-extension single-precision OP-FP flow: decode fields, read FP operands, perform FSUB semantics, then write rd.
rd
rs1
rs2
rm
fsub.s
,
,
,
Execution Context
FLEN=>=32 / fmt=S (00)
rounding: RNE nearest-even
fflags: example fflags remains 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00001
FSUB
00
fmt=S
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x08C58553
opcode
1010011 -> OP-FP
funct5/fmt
00001 + S(00) -> FSUB.S
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
7.5, 2.25
FP op
7.5 - 2.25 = 5.25
write
fa0(f10) = 5.25; example fflags remains 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; single-precision OP-FP instructions use opcode 1010011.
encoding: 0x08C58553
syntax : fsub.s fa0(f10), fa1(f11), fa2(f12), rne
result : fa0(f10) = 5.25; example fflags remains 0
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
Single-precision Calculation
rs1
fa1(f11) = 7.5
rs2
fa2(f12) = 2.25
result
7.5 - 2.25 = 5.25
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
This animation shows only F-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FSUB.S is an OP-FP arithmetic instruction from the RISC-V F extension. It reads two single-precision FP registers, rounds rs1-rs2 by rm/frm, and writes the result to FP register rd.
The .S suffix denotes the 32-bit single-precision floating-point format, using the F-extension OP-FP encoding.
The rm field selects a static rounding mode; rm=111 uses the dynamic frm rounding mode.
FSUB.S can accrue NV, OF, and NX; it does not produce DZ or UF. Static rm=101--110 and reserved dynamic-frm encodings have reserved behavior.
Cancellation between nearby operands is a numerical property; architecturally the result still follows single-precision subtraction, rounding mode, and fflags rules.
Common Usage Scenarios
Floating-point arithmetic
Understand this scenario with real code like «fsub.s f0, f1, f2 # f0 = f1-f2 (RNE)».
Numerical computing
Understand this scenario with real code like «fsub.s f0, f1, f2 # f0 = f1-f2 (RNE)».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register receiving the formatted result.
- rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
- Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
- Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.
Pitfalls / Common Confusions
rd, rs1, and rs2 are floating-point registers, not integer x registers.
Nearby operands may cancel numerically, but the architectural operation is still single-precision rs1-rs2 plus rounding.
Floating-point exceptions are recorded in fflags; do not explain FSUB.S with integer condition codes or integer overflow traps.
FAQ
How does rm affect the result?
rm selects the rounding mode, or uses frm for the dyn encoding. For inexact results, the rounding mode affects the written value and may set fflags.
Do floating-point exceptions trap like integer exceptions?
The F extension records floating-point exception flags in fflags; this page does not describe them as integer condition codes or integer overflow traps.