Does FROUND.D write an integer register?
No. The result is written to floating-point register f[rd]; the floating-point value is integral.
FROUND.D
RISC-V FROUND.D Instruction Details
Instruction ManualR-typeRound a double-precision floating-point value to an integral value in the same FP format, without setting NX.
Instruction Syntax
fround.d rd, rs1[, rm]
Operand Breakdown
rd, rs1: FP registers f0–f31 or ABI names; f0 is writable and rd may overlap rs1. rs1 is the only source; rs2=00100 is a fixed selector.
Optional rm defaults to dyn; 111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
ZfaDFP Precision
Instruction Behavior
FROUND.D requires RV32/RV64 Zfa+D and enabled FP state. It rounds f[rs1] to an integral value according to rm and writes it in D format to f[rd]. Zero and infinity are copied unchanged. NaN results are canonical; signaling NaN also accrues NV. It sets no NX, DZ, OF or UF and does not clear existing fflags.
FROUND.D Decode And Execute Animation
Shows the Zfa + D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FROUND semantics, then write rd.
rd
rs1
rm
fround.d
,
,
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
Execution Context
FLEN>=64 / fmt=D (01)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FROUND
01
fmt=D
00100
rs2=4 (roundToIntegral)
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x42458553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + D(01) -> FROUND.D
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / rs2=00100 (fixed)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.
encoding: 0x42458553
syntax : fround.d fa0(f10), fa1(f11), rne
result : Not written yet; initial fflags=0
This bounded teaching model computes whitelisted finite examples plus zero, infinity, and NaN; FROUND.D writes the integral value in D format. Zero and infinity are copied. FROUND does not set NX and sets no exception flags other than NV.
Double-precision Calculation
rs1
fa1(f11) = 1.5
result
Awaiting Execute
This bounded teaching model computes whitelisted finite examples plus zero, infinity, and NaN; FROUND.D writes the integral value in D format. Zero and infinity are copied. FROUND does not set NX and sets no exception flags other than NV.
Assumes Zfa + D, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Accepts the listed exact finite whitelist, signed zeros, infinity, qNaN, and sNaN. Rounding uses rm/frm; zero and infinity are copied, and sNaN sets NV. FROUND does not set NX. rd may overlap rs1, and f0 accepts writeback. Steps are teaching views.
This animation shows only Zfa + D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FROUND.D rounds a D value to an integral value in an FP register. It deliberately does not set NX; FROUNDNX.D sets NX when a non-NaN input differs from the rounded result.
Requires Zfa 1.0 and D; Zfa depends on F. rd and rs1 are FP registers f0–f31; f0 is writable and rd may overlap rs1.
32-bit OP-FP: funct5=01000, fmt=01 (D), rs2=00100, rs1, rm, rd, opcode=1010011. rs2 is a fixed selector, not a second source.
Optional rm defaults to dyn: 000/001/010/011/100 select rne/rtz/rdn/rup/rmm; 111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Operands narrower than FLEN must be correctly NaN-boxed; otherwise they are treated as canonical NaNs in their format. Narrower results get upper FLEN bits set to ones.
Zero and infinity are copied unchanged; NaN results are canonical and signaling NaN accrues NV. No NX or other flags are set; existing fflags are not cleared and setting a flag does not itself cause an FP exception trap.
The animation assumes valid NaN-boxing and initial fflags=0. It accepts the listed exact finite whitelist plus signed zeros, infinity, qNaN and sNaN; arbitrary decimal inputs are not simulated.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Zfa 1.0, §26.3The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F 2.2, §§21.2–21.3; D 2.2, §§22.2/22.5RISC-V Assembly Programmer's Manual — Floating-point rounding modesRISC-V ABIs Specification — Version 1.0, floating-point register convention
Common Usage Scenarios
Floating-Point Rounding
Assume RV32/RV64 Zfa+D, enabled FP state, f11=1.5 as a validly NaN-boxed D value if FLEN is wider, and initial fflags=0: fround.d f10, f11, rup writes f10=2.0 in an FP register, without setting NX; fflags remains 0.
Numeric Format Handling
Assume RV32/RV64 Zfa+D, enabled FP state, f11=1.5 as a validly NaN-boxed D value if FLEN is wider, and initial fflags=0: fround.d f10, f11, rup writes f10=2.0 in an FP register, without setting NX; fflags remains 0.
Pre-Use Checklist
Syntax Check
- rd, rs1: FP registers f0–f31 or ABI names; f0 is writable and rd may overlap rs1. rs1 is the only source; rs2=00100 is a fixed selector.
- Optional rm defaults to dyn; 111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Semantic Check
- Confirm Zfa+D, enabled FP state, and a correctly NaN-boxed D source in wider FLEN.
- The result remains a D floating-point value; only sNaN adds NV, with no NX, DZ, OF or UF. Existing fflags are preserved.
Pitfalls / Common Confusions
FROUND does not set NX; use FROUNDNX when inexact reporting is needed.
The result stays in an FP register; for an integer-register result use FCVT.W[U].D, or FCVT.L[U].D on RV64 only.
rm controls the direction for rounding to an integral value.
FAQ
How does FROUND.D differ from the other FROUND form?
FROUND does not set NX; FROUNDNX sets NX only when the input differs from the rounded result and is not NaN.