Does FROUNDNX.D write an integer register?
No. The result is written to FP register f[rd] in the original precision; zero, infinity and NaN follow the special rules listed on this page.
FROUNDNX.D
RISC-V FROUNDNX.D Instruction Details
Instruction ManualR-typeRound a double-precision floating-point value to an integral value in the same FP format; set NX only when the input differs from the rounded result and is not NaN.
Instruction Syntax
froundnx.d rd, rs1[, rm]
Operand Breakdown
rd, rs1: FP registers f0–f31 or ABI names; f0 is writable and rd may overlap rs1.
rs1 is the only source; rs2=00101 is a fixed selector. Optional rm defaults to dyn; 111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
ZfaDFP Precision
Instruction Behavior
FROUNDNX.D requires RV32/RV64 Zfa+D and enabled FP state. It rounds the double-precision value in f[rs1] to an integral value according to rm and writes it in D format to f[rd]. Zero and infinity are copied unchanged. NaN results are canonical; signaling NaN accrues NV. It accrues NX only when a non-NaN input differs from the rounded result. It sets no DZ, OF or UF and does not clear existing fflags.
FROUNDNX.D Decode And Execute Animation
Shows the Zfa + D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FROUNDNX semantics, then write rd.
rd
rs1
rm
froundnx.d
,
,
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
Execution Context
FLEN>=64 / fmt=D (01)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
01000
FROUNDNX
01
fmt=D
00101
rs2=5 (roundToIntegralExact)
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x42558553
opcode
1010011 -> OP-FP
funct5/fmt
01000 + D(01) -> FROUNDNX.D
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / rs2=00101 (fixed)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.
encoding: 0x42558553
syntax : froundnx.d fa0(f10), fa1(f11), rne
result : Not written yet; initial fflags=0
This bounded teaching model computes whitelisted finite examples plus zero, infinity, and NaN; FROUNDNX.D writes the integral value in D format. Zero and infinity are copied. NX is set when the input differs from the rounded result and is not NaN.
Double-precision Calculation
rs1
fa1(f11) = 1.5
result
Awaiting Execute
This bounded teaching model computes whitelisted finite examples plus zero, infinity, and NaN; FROUNDNX.D writes the integral value in D format. Zero and infinity are copied. NX is set when the input differs from the rounded result and is not NaN.
Assumes Zfa + D, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Accepts the listed exact finite whitelist, signed zeros, infinity, qNaN, and sNaN. Rounding uses rm/frm; zero and infinity are copied, and sNaN sets NV. NX is set when a non-NaN input differs from the rounded result. rd may overlap rs1, and f0 accepts writeback. Steps are teaching views.
This animation shows only Zfa + D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FROUNDNX.D rounds a double-precision value to an integral value in an FP register. It accrues NX only when a non-NaN input differs from the rounded result. It does not convert to an integer register.
Requires Zfa 1.0 and D; Zfa depends on F. rd and rs1 are FP registers f0–f31; f0 is writable and rd may overlap rs1.
32-bit OP-FP: funct5=01000, fmt=01 (D), rs2=00101, rs1, rm, rd, opcode=1010011. rs2 is a fixed selector, not a second source.
Optional rm defaults to dyn: 000/001/010/011/100 select rne/rtz/rdn/rup/rmm; 111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Operands narrower than FLEN must be correctly NaN-boxed; otherwise they are treated as canonical NaNs in their format. Narrower results get their upper FLEN minus format-width bits set to ones.
Zero and infinity are copied unchanged; NaN results are canonical and signaling NaN accrues NV. It accrues NX only when a non-NaN input differs from the rounded result. No DZ, OF or UF is set; existing fflags are not cleared and setting a flag does not itself cause an FP exception trap.
The animation assumes valid NaN-boxing and initial fflags=0. It accepts the listed exact finite whitelist plus signed zeros, infinity, qNaN and sNaN; arbitrary decimal inputs are not simulated.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Zfa 1.0 §26.3; F 2.2 §§21.2–21.3The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, D §22.2; H/Q formats and conversionsThe RISC-V Instruction Set Manual, Volume II: Privileged Architecture — Version 20260120, §3.1.6.7RISC-V Assembly Programmer’s Manual — cover v0.0.0, 2025-02-05; release v0.0.1, Floating-point rounding modesRISC-V ABIs Specification — Version 1.0, §1.2 Table 2
Common Usage Scenarios
Floating-Point Rounding
Assume required extensions and FP state enabled, f11=1.5 in this format (validly NaN-boxed when narrower than FLEN), and initial fflags=0: the rne example writes f10=2.0 in an FP register; the changed value sets NX=1.
Numeric Format Handling
Assume required extensions and FP state enabled, f11=1.5 in this format (validly NaN-boxed when narrower than FLEN), and initial fflags=0: the rne example writes f10=2.0 in an FP register; the changed value sets NX=1.
Pre-Use Checklist
Syntax Check
- rd, rs1: FP registers f0–f31 or ABI names; f0 is writable and rd may overlap rs1.
- rs1 is the only source; rs2=00101 is a fixed selector. Optional rm defaults to dyn; 111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
Semantic Check
- Confirm Zfa, the matching precision extension, enabled FP state, and valid NaN-boxing for narrower sources.
- The result stays in the same FP format. Zero and infinity are copied; NaN results are canonical, and sNaN adds NV. NX is added only when a non-NaN input differs from the rounded result. No DZ, OF or UF is added; existing fflags are preserved.
Pitfalls / Common Confusions
FROUNDNX sets NX only when the input differs from the rounded result and is not NaN; do not confuse it with FROUND, which does not set NX.
The result stays in an FP register; for an integer-register result use FCVT.W[U].D, or FCVT.L[U].D on RV64 only.
rm controls the direction for rounding to an integral value.
FAQ
How does FROUNDNX.D differ from the other FROUND form?
FROUNDNX sets NX only when the input differs from the rounded result and is not NaN; FROUND does not set NX.