Keep rs1 double-precision exponent and significand fields and copy the rs2 sign; no rounding or fflags updates.
FSGNJ.D is a double-precision sign-injection instruction in D. With valid inputs in this format, non-sign bits come from rs1 and the sign is copied from rs2; it uses no rm, does not round, sets no FP exception flags, and does not canonicalize NaNs. Sources narrower than FLEN first undergo NaN-boxing checks: malformed upper bits make the source a canonical NaN in this format; narrower results get upper ones.
Shows the D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FSGNJ semantics, then write rd.
The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.
Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.
Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.
Assumes required extensions and FS enabled, valid NaN-boxing for narrower sources, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros and infinities are supported. NaN payload bit patterns are covered in static text; textual NaN animation inputs are not supported. Equal sources require one initial value; rd may overlap a source and f0 is writable. Steps are teaching views.
This animation shows only D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
FSGNJ.D copies only the rs2 sign; rs1 supplies the exponent and significand. With valid inputs in this format, 3.5 and -2 give -3.5, with existing fflags unchanged.
Assume required extensions and FP state enabled, f11=3.5 and f12=-2 in this format (validly NaN-boxed when narrower than FLEN), and initial fflags=0: the example writes f10=-3.5, keeping f11 non-sign bits and copying f12 sign; fflags remains 0.
Assume required extensions and FP state enabled, f11=3.5 and f12=-2 in this format (validly NaN-boxed when narrower than FLEN), and initial fflags=0: the example writes f10=-3.5, keeping f11 non-sign bits and copying f12 sign; fflags remains 0.
For valid inputs in this format, rs1 non-sign bits and NaN payload are preserved, and sNaN is not quieted; only the sign comes from rs2. Narrower-than-FLEN sources still undergo NaN-boxing checks, with malformed boxing treated as canonical NaN.
No. It is a bit-level sign operation in FP registers and does not perform rounded arithmetic or exception-flag paths.