Does FSGNJX.D change the NaN payload?
Validly NaN-boxed sources (or format width equal to FLEN) preserve the payload; only the sign follows the XOR rule. An improperly NaN-boxed source in wider FLEN is first replaced with canonical NaN.
FSGNJX.D
RISC-V FSGNJX.D Instruction Details
Instruction ManualR-typeThe result keeps rs1 exponent and significand fields, while the sign bit is the XOR of the rs1 and rs2 signs.
Instruction Syntax
fsgnjx.d rd, rs1, rs2
Operand Breakdown
rd, rs1, rs2: FP registers f0–f31 or ABI names; f0 is writable, destinations may overlap sources, and equal sources read one initial value.
No rm, immediate, or rs3; funct3=010 selects FSGNJX, keeping rs1 non-sign bits and XORing the two source signs.
DFloating-Point Arithmetic
Instruction Behavior
FSGNJX.D only recombines the sign bit of a double-precision floating-point encoding: exponent and significand fields come from rs1, while the sign bit is the XOR of the rs1 and rs2 signs. It performs no floating-point arithmetic, does not round, sets no floating-point exception flags, and does not canonicalize NaNs. When the format is narrower than FLEN, source upper bits must be all ones; an improperly NaN-boxed source is first treated as a canonical NaN in this format, and narrower results receive upper ones.
FSGNJX.D Decode And Execute Animation
Shows the D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FSGNJX semantics, then write rd.
rd
rs1
rs2
fsgnjx.d
,
,
Execution Context
FLEN>=64 / fmt=D (01)
funct3: XOR rs1/rs2 signs
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00100
FSGNJX
01
fmt=D
01100
rs2
01011
rs1
010
funct3=010
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x22C5A553
opcode
1010011 -> OP-FP
funct5/fmt
00100 + D(01) -> FSGNJX.D
funct3
010 -> XOR rs1/rs2 signs
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.
encoding: 0x22C5A553
syntax : fsgnjx.d fa0(f10), fa1(f11), fa2(f12)
result : Not written yet; initial fflags=0
Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.
Double-precision Calculation
rs1
fa1(f11) = 3.5
rs2
fa2(f12) = -2.0
result
Awaiting Execute
rs1 sign
0
rs2 sign
1
result sign
Awaiting Execute
other bits
exponent/significand from rs1
Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.
Assumes required extensions and FS enabled, valid NaN-boxing for narrower sources, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros and infinities are supported. NaN payload bit patterns are covered in static text; textual NaN animation inputs are not supported. Equal sources require one initial value; rd may overlap a source and f0 is writable. Steps are teaching views.
This animation shows only D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FSGNJX.D is a D-extension OP-FP sign-injection instruction. The key points are how funct5/fmt/funct3 identify FSGNJX.D, and that the result only replaces the sign bit without rounding or fflags updates.
32-bit OP-FP: opcode=1010011, funct5=00100, fmt=01, funct3=010; rd, rs1, rs2 select FP registers, with no rm, immediate, or rs3.
Valid 64-bit sources use result.sign=rs1.sign XOR rs2.sign; non-sign bits come from rs1. No rounding, NaN canonicalization, or fflags updates occur.
When the format is narrower than FLEN, source upper bits must be all ones; an improperly NaN-boxed source is first treated as a canonical NaN in this format, and narrower results receive upper ones.
Required extensions and FP state must be enabled; f0 is writable, destinations may overlap sources, and equal sources read one initial value.
RV32/RV64 D 2.2 (requires F), FLEN>=64.
Common Usage Scenarios
Sign Operations
Assume required extensions and enabled FP state, valid f11=3.5 and f12=-2 in this format, correct NaN-boxing when narrower than FLEN, and initial fflags=0: f10=-3.5, sign 0 XOR 1=1, with f11 non-sign bits; fflags remains 0.
Floating-Point Bit Manipulation
Assume required extensions and enabled FP state, valid f11=3.5 and f12=-2 in this format, correct NaN-boxing when narrower than FLEN, and initial fflags=0: f10=-3.5, sign 0 XOR 1=1, with f11 non-sign bits; fflags remains 0.
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: FP registers f0–f31 or ABI names; f0 is writable, destinations may overlap sources, and equal sources read one initial value.
- No rm, immediate, or rs3; funct3=010 selects FSGNJX, keeping rs1 non-sign bits and XORing the two source signs.
Semantic Check
- Require enabled extensions and FP state; narrower sources undergo NaN-boxing checks, using canonical NaN for malformed boxing.
- Valid sources keep rs1 non-sign bits with rs1.sign XOR rs2.sign; no rounding, sNaN quieting, or fflags updates. Narrower results get upper ones.
Pitfalls / Common Confusions
This is a bit-level sign operation, not floating add/subtract, compare, or numeric conversion.
The result exponent and significand fields come from rs1; do not treat rs2 as a full numeric source operand.
For validly NaN-boxed sources (or format width equal to FLEN), rs1 non-sign bits and NaN payload are preserved without quieting sNaN; existing fflags stay unchanged.
Equal valid source operands XOR their sign bits to zero, producing the absolute value.
When the format is narrower than FLEN, source upper bits must be all ones; an improperly NaN-boxed source is first treated as a canonical NaN in this format, and narrower results receive upper ones.
FAQ
Does FSGNJX.D set fflags?
No. It is a bit-level sign operation in FP registers and does not perform rounded arithmetic or exception-flag paths.