Does FSGNJX.D change the NaN payload?
No. Except for the sign-bit rule, rs1 exponent and significand fields are preserved; the instruction does not canonicalize NaNs.
FSGNJX.D
RISC-V FSGNJX.D Instruction Details
Instruction ManualR-typeThe result keeps rs1 exponent and significand fields, while the sign bit is the XOR of the rs1 and rs2 signs.
Instruction Syntax
fsgnjx.d rd, rs1, rs2
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
DFloating-Point Arithmetic
Instruction Behavior
FSGNJX.D only recombines the sign bit of a double-precision floating-point encoding: exponent and significand fields come from rs1, while the sign bit is the XOR of the rs1 and rs2 signs. It performs no floating-point arithmetic, does not round, sets no floating-point exception flags, and does not canonicalize NaNs.
FSGNJX.D Decode And Execute Animation
Shows the D-extension double-precision OP-FP flow: decode fields, read FP operands, perform FSGNJX semantics, then write rd.
rd
rs1
rs2
fsgnjx.d
,
,
Execution Context
FLEN=64 / fmt=D (01)
funct3: XOR rs1/rs2 signs
fflags: does not set fflags
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00100
FSGNJX
01
fmt=D
01100
rs2
01011
rs1
010
funct3=010
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x22C5A553
opcode
1010011 -> OP-FP
funct5/fmt
00100 + D(01) -> FSGNJX.D
funct3
010 -> XOR rs1/rs2 signs
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
3.5, -2.0
FP op
sign=sign(rs1)^sign(rs2), magnitude=rs1 -> -3.5
write
fa0(f10) = -3.5; does not set fflags
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; double-precision OP-FP instructions use opcode 1010011.
encoding: 0x22C5A553
syntax : fsgnjx.d fa0(f10), fa1(f11), fa2(f12)
result : fa0(f10) = -3.5; does not set fflags
Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.
Double-precision Calculation
rs1
fa1(f11) = 3.5
rs2
fa2(f12) = -2.0
result
sign=sign(rs1)^sign(rs2), magnitude=rs1 -> -3.5
rs1 sign
0
rs2 sign
1
result sign
0 xor 1 = 1
other bits
exponent/significand from rs1
Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.
This animation shows only D-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FSGNJX.D is an D-extension OP-FP sign-injection instruction. The key points are how funct5/fmt/funct3 identify FSGNJX.D, and that the result only replaces the sign bit without rounding or fflags updates.
OP-FP opcode=1010011, funct5=00100, fmt=D, and funct3=010 identify FSGNJX.D.
The result exponent and significand fields come from rs1; the sign bit is produced by the current instruction rule from rs2 or the rs1/rs2 sign relation.
These instructions do not use rm, do not set fflags, and do not canonicalize NaNs.
With rs2=rs1 they can express common FABS pseudo-instruction semantics; the page animation shows only the official bit-level rule.
Common Usage Scenarios
Sign Operations
Understand this scenario with real code like «fsgnjx.d f0, f1, f1 # FABS.D: f0 = |f1|».
Floating-Point Bit Manipulation
Understand this scenario with real code like «fsgnjx.d f0, f1, f1 # FABS.D: f0 = |f1|».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register receiving the formatted result.
- rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
- Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
- Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.
Pitfalls / Common Confusions
This is a bit-level sign operation, not floating add/subtract, compare, or numeric conversion.
The result exponent and significand fields come from rs1; do not treat rs2 as a full numeric source operand.
It does not set fflags and does not canonicalize NaNs or rewrite the payload.
rs2=rs1 is commonly used for FABS pseudo-instruction semantics.
FAQ
Does FSGNJX.D set fflags?
No. It is a bit-level sign operation in FP registers and does not perform rounded arithmetic or exception-flag paths.