RVOPcode
Home/Instructions/Float Sign Inject Neg Half
FSGNJN.H

RISC-V FSGNJN.H Instruction Details

Instruction ManualR-type

For valid inputs in this format, the half-precision result keeps rs1 non-sign bits and inverts the rs2 sign; existing fflags are unchanged.

Instruction Syntax

fsgnjn.h rd, rs1, rs2
Operand Breakdown
rd, rs1, rs2: FP registers f0–f31 or ABI names; f0 is writable, rd may overlap a source, and equal sources use one initial value.
No rm, immediate, or rs3; funct3=001 selects FSGNJN, keeping rs1 non-sign bits and inverting the rs2 sign.
ZfhFloating-Point Arithmetic
Related Search Terms
FSGNJN.H instructionRISC-V FSGNJN.Hfsgnjn.h syntaxfsgnjn.h encodingfsgnjn.h sign bitfsgnjn.h NaN payloadfsgnjn.h half-precision sign injection

Instruction Behavior

FSGNJN.H is a half-precision sign-injection instruction in Zfh: keep the exponent and significand of valid rs1 and invert the sign of valid rs2. It does not round, add FP exception flags, quiet sNaNs, or canonicalize valid NaNs. Sources narrower than FLEN first undergo NaN-boxing checks: malformed upper bits make the source a canonical NaN in this format; narrower results get upper ones.

FSGNJN.H Decode And Execute Animation

Shows the Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FSGNJN semantics, then write rd.

rd
rs1
rs2
fsgnjn.h
,
,
Execution Context
FLEN>=32 / fmt=H (10)
funct3: negate rs2 sign
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00100
FSGNJN
10
fmt=H
01100
rs2
01011
rs1
001
funct3=001
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x24C59553
opcode
1010011 -> OP-FP
funct5/fmt
00100 + H(10) -> FSGNJN.H
funct3
001 -> negate rs2 sign
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.

encoding: 0x24C59553
syntax : fsgnjn.h fa0(f10), fa1(f11), fa2(f12)
result : Not written yet; initial fflags=0

Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.

Half-precision Calculation
rs1
fa1(f11) = 3.5
rs2
fa2(f12) = -2.0
result
Awaiting Execute
rs1 sign
0
rs2 sign
1
result sign
Awaiting Execute
other bits
exponent/significand from rs1

Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.

Assumes required extensions and FS enabled, valid NaN-boxing for narrower sources, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros and infinities are supported. NaN payload bit patterns are covered in static text; textual NaN animation inputs are not supported. Equal sources require one initial value; rd may overlap a source and f0 is writable. Steps are teaching views.

This animation shows only Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FSGNJN.H inverts only the rs2 sign; rs1 supplies the other bits. With valid inputs in this format, 3.5 and -2 give 3.5, with existing fflags unchanged.

RV32/RV64 requires Zfh and enabled FP state; rd, rs1, rs2 select f0–f31, including writable f0.
32-bit OP-FP: funct5=00100, fmt=10, funct3=001, opcode=1010011; no rm or immediate.
Sources narrower than FLEN first undergo NaN-boxing checks: malformed upper bits make the source canonical NaN; narrower results get upper ones.
Valid source non-sign bits come from rs1; invert the rs2 sign. Valid sNaNs are not quieted and no fflags are added.
Bit example: valid rs1=0xFC01 (sNaN) and a negative rs2 give 0x7C01; non-sign bits and NV are preserved.
Requires full Zfh; the Zfhmin data-transfer and conversion subset does not include FSGNJN.H.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120

Common Usage Scenarios

Sign Operations

Assume required extensions and FP state enabled, f11=3.5 and f12=-2 in this format (validly NaN-boxed when narrower than FLEN), and initial fflags=0: the example writes f10=3.5, keeping f11 non-sign bits and inverting f12 sign; fflags remains 0.

Floating-Point Bit Manipulation

Assume required extensions and FP state enabled, f11=3.5 and f12=-2 in this format (validly NaN-boxed when narrower than FLEN), and initial fflags=0: the example writes f10=3.5, keeping f11 non-sign bits and inverting f12 sign; fflags remains 0.

Pre-Use Checklist

Syntax Check
  • rd, rs1, rs2: FP registers f0–f31 or ABI names; f0 is writable, rd may overlap a source, and equal sources use one initial value.
  • No rm, immediate, or rs3; funct3=001 selects FSGNJN, keeping rs1 non-sign bits and inverting the rs2 sign.
Semantic Check
  • Confirm required extensions and enabled FP state. Narrower-than-FLEN sources undergo NaN-boxing checks; malformed boxing is treated as canonical NaN.
  • For valid sources, non-sign bits come from rs1; invert the rs2 sign. No rounding, sNaN quieting, or fflags updates. Narrower results get upper ones.

Pitfalls / Common Confusions

This operates on FP encoding signs, not FP arithmetic, comparison, or numeric conversion.
rs1 supplies non-sign bits; only invert the rs2 sign, not its numeric magnitude.
NaN payload preservation requires valid inputs in this format; malformed NaN-boxing first replaces the source with canonical NaN.
No rm, immediate, or rs3; valid sNaNs are not quieted and do not set NV. Existing fflags are preserved.

FAQ

Does FSGNJN.H change a NaN payload?

For valid inputs in this format, rs1 non-sign bits and NaN payload are preserved and sNaN is not quieted; invert the rs2 sign. Narrower-than-FLEN sources still undergo NaN-boxing checks, with malformed boxing treated as canonical NaN.

Does FSGNJN.H set fflags?

No. It does not use rm, round, or add FP exception flags; existing fflags are preserved. FP state must be enabled.