Does FSGNJX.Q change a NaN payload?
It does not canonicalize a NaN payload. Apart from the sign bit generated by the current instruction rule, the result exponent and significand fields come from rs1.
FSGNJX.Q
RISC-V FSGNJX.Q Instruction Details
Instruction ManualR-typeFSGNJX.Q preserves the quad-precision non-sign bits from rs1 and forms the result sign from the XOR of rs1 and rs2 signs.
Instruction Syntax
fsgnjx.q rd, rs1, rs2
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
QFloating-Point Arithmetic
Instruction Behavior
FSGNJX.Q is a floating-point sign-injection instruction in the Q format. The result exponent and significand fields come from rs1, while the sign bit is formed from the XOR of rs1 and rs2 signs; it performs no numeric conversion, does not round, sets no fflags, and does not canonicalize NaN payloads.
FSGNJX.Q Decode And Execute Animation
Shows the Q-extension quad-precision OP-FP flow: decode fields, read FP operands, perform FSGNJX semantics, then write rd.
rd
rs1
rs2
fsgnjx.q
,
,
Execution Context
FLEN=128 / fmt=Q (11)
funct3: XOR rs1/rs2 signs
fflags: does not set fflags
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00100
FSGNJX
11
fmt=Q
01100
rs2
01011
rs1
010
funct3=010
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x26C5A553
opcode
1010011 -> OP-FP
funct5/fmt
00100 + Q(11) -> FSGNJX.Q
funct3
010 -> XOR rs1/rs2 signs
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
3.5, -2.0
FP op
sign=sign(rs1)^sign(rs2), magnitude=rs1 -> -3.5
write
fa0(f10) = -3.5; does not set fflags
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; quad-precision OP-FP instructions use opcode 1010011.
encoding: 0x26C5A553
syntax : fsgnjx.q fa0(f10), fa1(f11), fa2(f12)
result : fa0(f10) = -3.5; does not set fflags
Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.
Quad-precision Calculation
rs1
fa1(f11) = 3.5
rs2
fa2(f12) = -2.0
result
sign=sign(rs1)^sign(rs2), magnitude=rs1 -> -3.5
rs1 sign
0
rs2 sign
1
result sign
0 xor 1 = 1
other bits
exponent/significand from rs1
Sign injection only recombines the floating-point sign bit: exponent and significand fields come from rs1, while the sign bit follows the current instruction rule from rs2 or the rs1/rs2 sign relation; it does not round or canonicalize NaNs.
This animation shows only Q-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FSGNJX.Q is mainly about where the sign bit comes from. It only changes the result-sign rule while keeping rs1 exponent and significand as the non-sign result fields, so it does not round or set exception flags.
The OP-FP fields use the Q format; funct5=00100, with funct3 selecting FSGNJ/FSGNJN/FSGNJX.
The non-sign result bits come from rs1, and the sign bit is determined by the current mnemonic from rs2 or from the rs1/rs2 sign relation.
With rs2=rs1 the instruction can express common FABS pseudo-instruction semantics; this assembly-level relation does not change the real instruction behavior.
Common Usage Scenarios
Sign Operations
Understand this scenario with real code like «fsgnjx.q f0, f1, f2 # f0 = f1 XOR sign of f2».
Floating-Point Bit Manipulation
Understand this scenario with real code like «fsgnjx.q f0, f1, f2 # f0 = f1 XOR sign of f2».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register receiving the formatted result.
- rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
- Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
- Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.
Pitfalls / Common Confusions
This recombines the sign bit of a floating-point encoding; it is not FP arithmetic, comparison, or integer/FP conversion.
The result exponent and significand fields come from rs1; rs2 only contributes sign-bit information.
FSGNJ-family instructions do not use rm, do not set fflags, and do not canonicalize NaN payloads.
With rs2=rs1 it is commonly used for FABS pseudo-instruction semantics, but the real encoding is still in the FSGNJ family.
FAQ
Does FSGNJX.Q set fflags?
No. The FSGNJ family performs sign injection, does not use rm, does not round, and does not set floating-point exception flags.