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FSGNJX.Q

RISC-V FSGNJX.Q Instruction Details

Instruction ManualR-type

The result keeps rs1 magnitude bits and takes its sign from the XOR of rs1 and rs2 signs.

Instruction Syntax

fsgnjx.q rd, rs1, rs2
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
QFloating-Point Arithmetic
Related Search Terms
FSGNJX.Q instructionRISC-V FSGNJX.Qfsgnjx.q syntaxfsgnjx.q sign bitfsgnjx.q NaN behaviorquad-precision sign injection

Instruction Behavior

FSGNJX.Q only recombines the sign bit of a quad-precision floating-point encoding: exponent and significand fields come from rs1, while the sign is produced from the XOR of rs1 and rs2 signs. It performs no floating-point arithmetic, does not round, sets no floating-point exception flags, and does not canonicalize NaNs.

Quick Understanding & Search Notes

FSGNJX.Q answers searches such as why floating negate/absolute/copy does not raise exceptions. It only manipulates sign-bit information and leaves rs1 exponent and significand bits unchanged.

With rs2=rs1, FSGNJ/FSGNJN/FSGNJX correspond to common FMV/FNEG/FABS pseudo-instruction semantics.
These instructions have no rm field and do not set fflags.
RISC-V Unprivileged ISA Manual: Q Extension

Common Usage Scenarios

Sign Operations

Understand this scenario with real code like «fsgnjx.q f0, f1, f2 # f0 = f1 XOR sign of f2».

Floating-Point Bit Manipulation

Understand this scenario with real code like «fsgnjx.q f0, f1, f2 # f0 = f1 XOR sign of f2».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This is a bit-level sign operation, not arithmetic or numeric conversion.
It sets no exception flags and does not canonicalize NaNs.
rs2=rs1 is commonly used for the FABS pseudo-instruction.

FAQ

Does FSGNJX.Q change the NaN payload?

It does not canonicalize NaNs; except for the sign bit rule, the remaining rs1 bits are preserved.

Is FSGNJX.Q a numeric conversion?

No. It is a bit-level sign operation inside floating-point registers.