When is execution legal?
At the supported XLEN, with H implemented: M/HS or V=0 U-mode with HU=1 may execute. V=0 U-mode with HU=0 raises illegal-instruction; V=1 raises virtual-instruction.
HSV.D
RISC-V HSV.D Instruction Details
Instruction ManualSYSTEM R-type fieldsHypervisor virtual-machine store of a doubleword using VS/VU effective privilege and two-stage translation.
Instruction Syntax
hsv.d rs2, (rs1)
Operand Breakdown
H 1.0; RV64 only; 32-bit SYSTEM R-type fields, funct7=0110111, funct3=100, opcode=1110011.
rs2=[24:20] supplies the low 64 data bits, rs1=[19:15] directly supplies the address, and rd=[11:7] is fixed to 00000. No offset immediate.
M/HS or V=0 U-mode with HU=1 may execute; V=1 raises virtual-instruction, and V=0 U-mode with HU=0 raises illegal-instruction. SPVP=0/1 selects VU/VS access; HS SUM is ignored and MPRV does not alter the access.
rs2=x0 stores zero. If rs1=rs2, source data is the low bits of that same address register. The example does not update memory outside the access width.
Examples assume H is available, relevant modes use the same XLEN, pointer masking is disabled, and translation/protection succeeds. Misaligned completion depends on the execution environment.
HSystem & Privilege
Extension condition: H extension 1.0; RV64 only. V=0, in M/HS or U-mode with hstatus.HU=1.
Related Search Terms
Instruction Behavior
HSV.D is the H-extension virtual-machine store. It may execute in M-mode or HS-mode, or in U-mode when hstatus.HU=1. The explicit memory access uses effective privilege VU when hstatus.SPVP=0 and VS when hstatus.SPVP=1, with two-stage address translation. HSV.D is not valid for RV32.
HSV.D Decode And Execute Animation
Shows HSV.D SYSTEM decoding, privilege checks, two-stage translation, and 64-bit store commitment without modeling page walks or TLB implementation.
rs2
rs1
hsv.d,()
Assumes H is implemented, relevant privilege modes use the same XLEN, and pointer masking is disabled. Input represents low source bits; the selector supplies the access outcome without validating page tables. rs1=x0 fixes address zero. Steps are teaching stages, not processor cycles.
rs2=x0 fixes the source to zero. With rs1=rs2, source low bits derive from the same address register and cannot be edited independently. Both use pre-execution values. The stored number represents the full access width; byte endianness is not simulated.
31..25
24..20
19..15
14..12
11..7
6..0
0110111
funct7
01100
rs2/source
01011
rs1/address
100
PRIVM
00000
rd=00000
1110011
SYSTEM
Architectural Data Path
instruction
0x6EC5C073
decode
funct7=0110111, rs2=01100, funct3=100, rd=00000 -> HSV.D
address
a1(x11) -> 0x0000000040001000 (no immediate offset)
privilege
HS: execution permitted
translation
VU effective privilege -> VS-stage -> G-stage; HS SUM ignored; MPRV is not used
store
a2(x12) low 64 bits = 0x8000000000000001 -> memory[0x0000000040001000]
state
Architectural state is not committed; the final memory state is shown only at writeback.
Architectural state is not committed; the final memory state is shown only at writeback.
This animation shows only official architectural conditions and outcomes; page walks, TLBs, caches, and platform exception handling are not modeled.
Quick Understanding & Search Notes
Address=rs1 (no offset). Success: store rs2[63:0] to memory; no rd write.
SPVP=0/1 selects VU/VS. HS-level SUM is ignored; MPRV has no effect.
rs2=x0 stores zero; rs1=rs2 uses the same register value for address and source.
Common Usage Scenarios
Guest memory writes
RV64 H, HS-mode, SPVP=0, pointer masking off, address 0x1000 and a successful access: a0=0x1000 and a1=0x8000000000000001; hsv.d a1, (a0) writes 0x8000000000000001 to 8 bytes at that address.
Pre-Use Checklist
Syntax Check
- H 1.0; RV64 only; 32-bit SYSTEM R-type fields, funct7=0110111, funct3=100, opcode=1110011.
- rs2=[24:20] supplies the low 64 data bits, rs1=[19:15] directly supplies the address, and rd=[11:7] is fixed to 00000. No offset immediate.
Semantic Check
- M/HS or V=0 U-mode with HU=1 may execute; V=1 raises virtual-instruction, and V=0 U-mode with HU=0 raises illegal-instruction. SPVP=0/1 selects VU/VS access; HS SUM is ignored and MPRV does not alter the access.
- rs2=x0 stores zero. If rs1=rs2, source data is the low bits of that same address register. The example does not update memory outside the access width.
- Examples assume H is available, relevant modes use the same XLEN, pointer masking is disabled, and translation/protection succeeds. Misaligned completion depends on the execution environment.
Pitfalls / Common Confusions
Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
U-mode execution is legal only when hstatus.HU=1; otherwise it raises illegal-instruction.
Access faults, guest-page faults, and page faults are still possible under the VS/G-stage translations.