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HSV.H

RISC-V HSV.H Instruction Details

Instruction ManualSYSTEM R-type fields

Hypervisor virtual-machine store of a halfword using VS/VU effective privilege and two-stage translation.

Instruction Syntax

hsv.h rs2, (rs1)
Operand Breakdown
This is a SYSTEM R-type fields-format instruction. Confirm operand positions based on the assembly syntax.
HSystem & Privilege
Related Search Terms
HSV.H instructionRISC-V HSV.Hhsv.h syntaxhsv.h encodinghsv.h Hhsv.h virtual storehsv.h VS-stage

Instruction Behavior

HSV.H is the H-extension virtual-machine store. It may execute in M-mode or HS-mode, or in U-mode when hstatus.HU=1. The explicit memory access uses effective privilege VU when hstatus.SPVP=0 and VS when hstatus.SPVP=1, with two-stage address translation.

HSV.H Decode And Execute Animation

Shows HSV.H SYSTEM decoding, privilege checks, two-stage translation, and 16-bit store commitment without modeling page walks or TLB implementation.

rs2
rs1
hsv.h
,(
)
31..25
24..20
19..15
14..12
11..7
6..0
0110011
funct7
01100
rs2/source
01011
rs1/address
100
PRIVM
00000
rd=00000
1110011
SYSTEM
Architectural Data Path
instruction
0x66C5C073
decode
funct7=0110011, rs2=01100, funct3=100, rd=00000 -> HSV.H
address
a1(x11) -> 0x0000000040001000 (no immediate offset)
privilege
HS: execution permitted
translation
VU effective privilege -> VS-stage -> G-stage; HS SUM ignored; MPRV is not used
store
a2(x12) low 16 bits = 0x8001 -> memory[0x0000000040001000]
state
Architectural state is not committed; the final memory state is shown only at writeback.
Architectural state is not committed; the final memory state is shown only at writeback.

This animation shows only official architectural conditions and outcomes; page walks, TLBs, caches, and platform exception handling are not modeled.

Quick Understanding & Search Notes

HSV.H is the H-extension virtual-machine halfword store, storing through VS-stage and G-stage translation using the memory access's VS/VU effective privilege.

Execution permission, trap type, and state restoration depend on privilege level, relevant CSR bits, and extension presence.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
RISC-V Privileged Architecture Manual, Hypervisor Extension

Common Usage Scenarios

Hypervisor Device Emulation

Understand this scenario with real code like «hsv.h a1, (a0)».

Guest Memory Access

Understand this scenario with real code like «hsv.h a1, (a0)».

Virtualized Instruction Simulation

Understand this scenario with real code like «hsv.h a1, (a0)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is SYSTEM R-type fields.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
U-mode execution is legal only when hstatus.HU=1; otherwise it raises illegal-instruction.
Access faults, guest-page faults, and page faults are still possible under the VS/G-stage translations.

FAQ

Is it a normal user-mode instruction?

No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.

Does it replace ordinary memory fences?

No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.