Can LW.AQ use offset(rs1)?
No. The official syntax is lw.aq rd, (rs1), with no offset immediate; the address comes directly from rs1.
LW.AQ
RISC-V LW.AQ Instruction Details
Instruction ManualR-typeZalasr atomic load of 4 bytes with acquire-RCsc ordering.
Instruction Syntax
lw.aq rd, (rs1)
Operand Breakdown
Destination rd: receives the sign-extended load result; if rd=x0, the writeback is discarded.
Address register rs1: directly supplies the memory address; Zalasr syntax has no offset immediate.
Encoding field rs2 is fixed to 00000; aq must be 1, and aq/rl only annotate ordering.
ZalasrCache & Synchronization
Instruction Behavior
LW.AQ is a 4-byte ordered atomic load in the Zalasr standalone load-acquire/store-release family. It atomically reads 32 bits from the address in x[rs1], sign-extends from that width, and writes x[rd]; the syntax has no offset field. The address is naturally aligned to the access width by default unless relaxed by the misaligned atomicity granule PMA.
LW.AQ Zalasr Decode And Execute Animation
Shows the Zalasr standalone load-acquire AMO encoding, no-offset address syntax, 32-bit data transfer, and aq/rl ordering annotation.
rd
rs1
lw.aq,()
Ordering Annotation
aq=1, rl=0 (acquire)
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00110
funct5
1
aq
0
rl
00000
rs2=00000
01010
rs1
010
funct3
00101
rd
0101111
opcode
Zalasr Data Path
instruction
0x340522AF
opcode
0101111 -> AMO major opcode
funct5
00110 -> LW.AQ
aq / rl
1/0 -> acquire
operands
rd=t0(x5), rs1=a0(x10)
address
a0(x10) -> 0x00001000 (no offset)
memory read
mem[0x00001000] -> 0x80000002
execute
sign_extend(0x80000002, 32) -> 0x80000002
writeback
t0(x5) = 0x80000002
32-bit Transfer View
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0
memory 32
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LW.AQ loads 32 bits from memory and sign-extends from that width to XLEN before writing rd.
This animation shows ISA-visible Zalasr atomic load/store behavior and aq/rl ordering annotations; it does not model LR/SC reservations, AMO read-modify-write old-value return, caches, buses, or pipeline timing.
Quick Understanding & Search Notes
LW.AQ uses rs1 directly as the address, atomically reads 4 bytes, and sign-extends into rd; aq/rl bits provide ordering annotations and do not change the loaded data.
The syntax is lw.aq rd, (rs1), with no offset field; the address comes from x[rs1].
funct5=00110 selects the Zalasr load-acquire class, funct3=010 selects the LW.AQ access width, the AMO major opcode is 0101111, and the aq bit must be 1 for Zalasr loads.
The 32-bit loaded value is sign-extended from the source width to XLEN.
aq/rl describe memory ordering only; they do not change the load, sign extension, or rd=x0 architectural behavior.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «lw.aq x5, (x6)».
Concurrency & Multi-core
Understand this scenario with real code like «lw.aq x5, (x6)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The syntax has no offset immediate; the address comes directly from rs1.
The load result is sign-extended from the 32-bit source width to XLEN; Zalasr has no unsigned load form.
Zalasr load encodings without aq set are RESERVED.
Zalasr is a single ordered atomic load/store instruction, not an LR/SC reservation protocol or an AMO read-modify-write old-value return.
FAQ
Is LW.AQ an LR/SC or AMO read-modify-write operation?
No. These Zalasr instructions are single ordered atomic load/store operations; the animation does not show reservations or old-value return.
Do aq/rl bits change the data result?
No. aq/rl are ordering annotations; the loaded value is still sign-extended from the source width into rd.