Can LW.AQ use offset(rs1)?
No. The official syntax is rd,(rs1) or rs2,(rs1), with no offset field.
LW.AQ
RISC-V LW.AQ Instruction Details
Instruction ManualI-typeZalasr atomic load of 4 bytes with acquire-RCsc ordering.
Instruction Syntax
lw.aq rd, (rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZalasrCache & Synchronization
Instruction Behavior
LW.AQ is a standalone Zalasr atomic load-acquire instruction. It atomically loads 4 bytes from the address in x[rs1] and sign-extends the value to x[rd]. The address must be naturally aligned to the operand width unless relaxed by the misaligned atomicity granule PMA;
Quick Understanding & Search Notes
LW.AQ is a standalone ordered atomic Zalasr load; rs1 is the only address source and there is no ordinary load/store offset field.
Results are always sign-extended; LD.AQ/LD.AQRL are RV64-only.
Natural alignment is the default requirement, optionally relaxed by PMA.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «lw.aq x5, (x6)».
Concurrency & Multi-core
Understand this scenario with real code like «lw.aq x5, (x6)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The syntax has no offset immediate; the address comes directly from rs1.
The loaded result is always sign-extended to XLEN; there is no unsigned Zalasr load form.
Load encodings without aq set are RESERVED.
Zalasr provides ordered atomic load/store operations, not an LR/SC pair protocol.
FAQ
Is LW.AQ just a normal load/store plus fence?
No. It is a single atomic ordered load/store instruction defined by Zalasr.