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NTL.S1

RISC-V NTL.S1 Instruction Details

Instruction ManualR-type HINT (ADD x0, x0, x4)

Zihintntl innermost-shared-cache non-temporal locality hint for the immediately following explicit memory-access target instruction.

Instruction Syntax

ntl.s1
Operand Breakdown
This is a R-type HINT (ADD x0, x0, x4)-format instruction. Confirm operand positions based on the assembly syntax.
ZihintntlMicroarch HintsCache & Sync
Related Search Terms
ntl.s1 instructionRISC-V ntl.s1ntl.s1 syntaxntl.s1 encodinginnermost shared cachentl.s1 Zihintntlntl.s1 cache hint

Instruction Behavior

NTL.S1 is a Zihintntl non-temporal locality HINT encoded as ADD x0, x0, x4. It indicates that the explicit memory accesses of the immediately following target instruction do not exhibit temporal locality within the capacity of the innermost level of shared cache in the memory hierarchy. The hint changes no architectural state and does not alter the architecturally visible effects of the target instruction; implementations may freely ignore it. NTL affects all memory-access instructions except Zicbom cache-management instructions, and it can also apply to Zicbop prefetch hints.

NTL.S1 Decode Animation

Decodes the ADD fields and shows target-instruction conditions and architectural boundaries.

ntl.s1
31..25
24..20
19..15
14..12
11..7
6..0
0000000
funct7
00100
rs2=x4
00000
rs1=x0
000
funct3
00000
rd=x0
0110011
OP
instruction
ntl.s1 = 0x00400033
opcode
0110011 -> OP/ADD encoding
fixed fields
funct7=0000000, funct3=000, rd=x0, rs1=x0, rs2=x4
target
explicit memory access
hint
may hint that this access has no exploitable temporal locality in the innermost shared cache
architectural state
NTL and the target instruction's architecturally visible effects are unchanged; the implementation may ignore the HINT

This animation shows only NTL architectural semantics from the unprivileged ISA; it does not infer a specific cache hierarchy, allocation policy, timing, or performance result.

Quick Understanding & Search Notes

NTL.S1 is a non-temporal locality prefix HINT that describes expected reuse of the next explicit memory access, without changing that access's architectural semantics.

The four NTL variants differ only in cache-level scope: P1, PALL, S1, and ALL.
If the target instruction traps, the official recommendation is not to apply the NTL to the first instruction in the trap handler.
RISC-V Unprivileged ISA Manual: Zihintntl non-temporal locality hints

Common Usage Scenarios

Cache & Hints

Understand this scenario with real code like «ntl.s1».

Concurrency & Multi-core

Understand this scenario with real code like «ntl.s1».

Performance

Understand this scenario with real code like «ntl.s1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type HINT (ADD x0, x0, x4).
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

It applies only to the immediately following target instruction; later memory accesses are not governed by this NTL prefix.
This is a HINT and may be ignored; it must not be used as a correctness, synchronization, or consistency mechanism.
The official text discourages following NTL with an instruction that does not explicitly access memory; doing so has no architecturally visible effect but may reduce performance.
NTL does not affect Zicbom CBO.CLEAN/CBO.FLUSH/CBO.INVAL, but can affect other explicit memory accesses and prefetch hints.

FAQ

Does NTL.S1 change the result of the next load/store?

No. It does not alter the architecturally visible effects of the target instruction.

Can NTL.S1 be ignored by an implementation?

Yes. It is a HINT, so software cannot rely on it for performance or correctness guarantees.