Can SB.RL use offset(rs1)?
No. The official syntax is sb.rl rs2, (rs1), with no offset immediate; the address comes directly from rs1.
SB.RL
RISC-V SB.RL Instruction Details
Instruction ManualAMOZalasr atomic store of 1 byte with release-RCsc ordering.
Instruction Syntax
sb.rl rs2, (rs1)
Operand Breakdown
Source rs2: supplies the low bits written to memory; the B/H/W/D form selects the width.
Address register rs1: directly supplies the memory address; Zalasr syntax has no offset immediate.
Encoding field rd is fixed to 00000/x0; rl must be 1, and aq/rl only annotate ordering.
ZalasrCache & Synchronization
Instruction Behavior
SB.RL is a 1-byte ordered atomic store in the Zalasr standalone load-acquire/store-release family. It atomically writes the low 8 bits of x[rs2] to the address in x[rs1]; the syntax has no offset field, and rd is fixed to x0 in the encoding. A 1-byte access is naturally aligned at every byte address.
SB.RL Zalasr Decode And Execute Animation
Shows the Zalasr standalone store-release AMO encoding, no-offset address syntax, 8-bit data transfer, and aq/rl ordering annotation.
rs2
rs1
sb.rl,()
Execution Context
A 1-byte access is naturally aligned at every byte address.
Assume implemented Zalasr and successful permitted fetch/data access except for the shown alignment exception. Demo addresses are nonnegative safe integers (at most 2^53−1), also fitting 32 bits on RV32. An x0 source is zero; rs2=rs1 uses one register value.
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00111
funct5
0
aq
1
rl
01011
rs2
01010
rs1
000
funct3
00000
rd=00000
0101111
opcode
Zalasr Data Path
instruction
0x3AB5002F
opcode
0101111 -> AMO major opcode
funct5
00111 -> SB.RL
aq / rl
0/1 -> release
operands
rs2=a1(x11), rs1=a0(x10), rd=x0
address
a0(x10) -> 0x00001000 (no offset); naturally aligned
store source
low 8 bits of a1(x11) -> 0x7F
execute
atomic store 8 bits at 0x00001000
writeback
mem[0x00001000] = 0x7F
8-bit Transfer View
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
rs2 low 8
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-
-
-
-
-
-
-
SB.RL writes only the low 8 bits of rs2 to memory; higher rs2 bits are not part of the stored value.
This animation shows ISA-visible Zalasr atomic load/store behavior and aq/rl ordering annotations; it does not model LR/SC reservations, AMO read-modify-write old-value return, caches, buses, or pipeline timing.
Quick Understanding & Search Notes
SB.RL uses rs1 directly as the address and atomically writes the low 8 bits of rs2; aq/rl bits provide ordering annotations and do not change the stored data.
The syntax is sb.rl rs2, (rs1), with no offset field; the address comes from x[rs1].
funct5=00111 selects the Zalasr store-release class, funct3=000 selects the SB.RL access width, the AMO major opcode is 0101111, SB.RL fixes aq=0 and rl=1, and rd is fixed to x0.
The stored value comes from the low 8 bits of x[rs2].
aq/rl describe memory ordering only; they do not change the stored data and do not return the old memory value.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «sb.rl x5, (x6)».
Concurrency & Multi-core
Understand this scenario with real code like «sb.rl x5, (x6)».
Pre-Use Checklist
Syntax Check
- Verify source rs2 and address register rs1; the syntax has no offset.
- Verify rd is fixed to x0 in the encoding; the instruction does not return the old memory value.
Semantic Check
- Verify that the stored value uses the low bits of rs2 at the B/D width.
- Verify Zalasr support; a 1-byte access is naturally aligned at every byte address.
- Verify that release-RCsc ordering with aq=0 and rl=1 matches the intended use.
Pitfalls / Common Confusions
The syntax has no offset immediate; the address comes directly from rs1.
The store uses only the low 8 bits of rs2; higher bits are not part of the written value.
Zalasr store encodings without rl set are RESERVED.
Zalasr is a single ordered atomic load/store instruction, not an LR/SC reservation protocol or an AMO read-modify-write old-value return.
FAQ
Is SB.RL an LR/SC or AMO read-modify-write operation?
No. These Zalasr instructions are single ordered atomic load/store operations; the animation does not show reservations or old-value return.
Do aq/rl bits change the data result?
No. aq/rl are ordering annotations; the stored value is still the low 8 bits of rs2.