Can SD.AQRL use offset(rs1)?
No. The official syntax is rd,(rs1) or rs2,(rs1), with no offset field.
SD.AQRL
RISC-V SD.AQRL Instruction Details
Instruction ManualS-typeZalasr atomic store of 8 bytes with release+acquire-RCsc ordering (RV64-only).
Instruction Syntax
sd.aqrl rs2, (rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
ZalasrCache & Synchronization
Instruction Behavior
SD.AQRL is a standalone Zalasr atomic store-release instruction. It atomically stores the low 64 bits of x[rs2] to the address in x[rs1]. The address must be naturally aligned to the operand width unless relaxed by the misaligned atomicity granule PMA; D-width forms are RV64-only.
Quick Understanding & Search Notes
SD.AQRL is a standalone ordered atomic Zalasr store; rs1 is the only address source and there is no ordinary load/store offset field.
Stores take low bits from rs2; SD.RL/SD.AQRL are RV64-only.
Natural alignment is the default requirement, optionally relaxed by PMA.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «sd.aqrl x5, (x6)».
Concurrency & Multi-core
Understand this scenario with real code like «sd.aqrl x5, (x6)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
LD/SD aq/rl forms are RV64-only.
The store uses only the low bits of rs2; upper bits are ignored.
Store encodings without rl set are RESERVED.
Zalasr provides ordered atomic load/store operations, not an LR/SC pair protocol.
FAQ
Is SD.AQRL just a normal load/store plus fence?
No. It is a single atomic ordered load/store instruction defined by Zalasr.