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SHA256SUM0

RISC-V SHA256SUM0 Instruction Details

Instruction ManualI-type

SHA-256 Σ0 function (uppercase): ROTR(rs1,2) ^ ROTR(rs1,13) ^ ROTR(rs1,22)

Instruction Syntax

sha256sum0 rd, rs1
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZknhCrypto & Security

Instruction Encoding

31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode

SHA256SUM0 uses opcode 0010011 (0x13), funct3 001, funct7 0001010. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.

Format: I-type
opcode: 0010011 (0x13)
funct3: 001 (0x1)
funct7: 0001010 (0x0a)

Instruction Behavior

sha256sum0 implements SHA-256 compression Σ0 (uppercase): Σ0(x) = ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22). Reads rs1, computes Σ0, writes to rd. Used in SHA-256 compression A-register update.

Quick Understanding & Search Notes

SHA256SUM0 is a Zknh scalar cryptography instruction for SHA-256 transform. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.

sha256sum0 performs the SHA-256 uppercase Sigma compression transform using the official fixed rotate-right and logical-shift combination.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «sha256sum0 a0, a1».

Hash Algorithms

Understand this scenario with real code like «sha256sum0 a0, a1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Σ0 (sum0, uppercase) for compression; σ0 (sig0, lowercase) for message schedule. Different rotate/shift amounts.

FAQ

Does SHA256SUM0 use floating-point or vector registers?

No. These scalar crypto extension instructions use integer X registers.

Is SHA256SUM0 a complete algorithm implementation?

No. It is a low-level step from AES, SHA, SM3, or SM4; software still combines instructions with the algorithm schedule, round constants, or round keys.