Does SHA256SUM1 use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SHA-256 Σ1 function (uppercase): ROTR(rs1,6) ^ ROTR(rs1,11) ^ ROTR(rs1,25)
sha256sum1 implements the SHA-256 compression Σ1 function: Σ1(x) = ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25). It is defined for RV32/RV64: RV32 operates on all of X(rs1), while RV64 uses X(rs1)[31:0] and sign-extends the 32-bit result before writing rd.
Bounded teaching inputs execute the official SHA-256 fixed-width bit operations; this does not model a complete algorithm or microarchitecture.
SHA256SUM1 is defined in RV32/RV64; RV64 uses X(rs1)[31:0] and sign-extends the 32-bit result to XLEN.
This animation shows only official ISA fields and architectural state; it does not model a complete hash algorithm, pipeline, cache, or timing implementation.
SHA256SUM1 is a Zknh scalar cryptography instruction for SHA-256 transform. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
Understand this scenario with real code like «sha256sum1 a0, a1».
Understand this scenario with real code like «sha256sum1 a0, a1».
No. These scalar crypto extension instructions use integer X registers.
No. It implements one SHA-2 Sigma transform; software still schedules the remaining SHA-2 computation.