What register width does SHA256SUM1 use?
Zknh RV32/RV64: transform X(rs1)[31:0]. RV64 sign-extends the 32-bit result into rd. The upper source word is ignored.
SHA256SUM1
RISC-V SHA256SUM1 Instruction Details
Instruction ManualSHA2 OP-IMM fixed-selector fieldsSHA-256 Σ1: ror32(x,6) ^ ror32(x,11) ^ ror32(x,25)
Instruction Syntax
sha256sum1 rd, rs1
Syntax is sha256sum1 rd, rs1, with only two integer-register operands selecting x0–x31 or ABI names.
32-bit OP-IMM encoding: bits 31..20=000100000001, funct3=001, opcode=0010011; there is no assembly immediate.
RV32/RV64 Zknh (also included in Zkn/Zk); transform only the low 32 source bits and sign-extend the 32-bit result on RV64.
An x0 source is zero and writes to x0 are discarded; rd=rs1 reads the original source first. This instruction must have data-independent execution latency.
ZknhCrypto & Security
Instruction Behavior
sha256sum1 is the Zknh SHA-256 Σ1 transform: Σ1(x) = ror32(x,6) ^ ror32(x,11) ^ ror32(x,25). It is defined for RV32/RV64 with x = X(rs1)[31:0]. RV64 ignores the upper source word and sign-extends the 32-bit result into rd. These transforms also work for SHA2-224. Rotations stay within the input word width; >> is a zero-filling logical right shift.
SHA256SUM1 Decode And Execute Animation
Bounded teaching inputs execute the official SHA-256 fixed-width bit operations; this does not model a complete algorithm or microarchitecture.
rd
rs1
sha256sum1
,
Initially rd shares the source value when rd=rs1; otherwise the demo starts rd at 0. An rs1=x0 source always reads 0. SHA256SUM1 is defined in RV32/RV64; RV64 uses X(rs1)[31:0] and sign-extends the 32-bit result to XLEN.
fixed selector
source
fixed
destination
OP-IMM
31..20
000100000001
19..15
rs1=x11
14..12
001
11..7
rd=x10
6..0
0010011
Execution Data Path
inb
0x89ABCDEF
ror32(inb, 6)
0xBE26AF37
ror32(inb, 11)
0xBDF13579
ror32(inb, 25)
0xD5E6F7C4
result
0xD6316D8A
Architectural Result
a0(x10) = 0x00000000
This animation shows only official ISA fields and architectural state; it does not model a complete hash algorithm, pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
sha256sum1 reads one integer source, applies the fixed SHA-256 Σ1 formula, then writes rd. The input word and transform result are 32 bits; RV64 ignores the upper source word and sign-extends the result to 64 bits.
The 32-bit instruction fixes bits 31..20 to 000100000001 (0x101), funct3=001 and opcode=0010011; the syntax has no immediate.
An x0 source is zero; rd=x0 discards writeback, and rd=rs1 reads the source before writing it.
This instruction must have data-independent execution latency; animation steps do not represent CPU cycles.
Common Usage Scenarios
SHA-256 Σ1 transform
RV32/RV64 Zknh, x11=1: sha256sum1 x10, x11 applies the fixed formula on this page and yields x10=0x04200080. RV64 sign-extends this 32-bit result; its top bit is zero in this example.
Pre-Use Checklist
Syntax Check
- Syntax is sha256sum1 rd, rs1, with only two integer-register operands selecting x0–x31 or ABI names.
- 32-bit OP-IMM encoding: bits 31..20=000100000001, funct3=001, opcode=0010011; there is no assembly immediate.
Semantic Check
- RV32/RV64 Zknh (also included in Zkn/Zk); transform only the low 32 source bits and sign-extend the 32-bit result on RV64.
- An x0 source is zero and writes to x0 are discarded; rd=rs1 reads the original source first. This instruction must have data-independent execution latency.
Pitfalls / Common Confusions
σ0/σ1 and Σ0/Σ1 use different fixed formulas; 0/1 do not select the low/high input half.
Rotations use the fixed word width; a >> term is logical and does not replicate the sign bit.
RV64 sign-extends the result rather than zero-extending it; upper source bits are ignored.
FAQ
Is the fixed selector an immediate operand?
No. The syntax is sha256sum1 rd, rs1. Bits 31..20 select the transform; there is no assembly immediate.