Does SHA512SIG1L use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SHA512SIG1L
RISC-V SHA512SIG1L Instruction Details
Instruction ManualR-typeLow 32 bits of SHA-512 σ1 (RV32): compute σ1 from (rs1=hi, rs2=lo) and return bits[31:0]
Instruction Syntax
sha512sig1l rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZknhCrypto & Security
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
SHA512SIG1L uses opcode 0110011 (0x33), funct3 110, funct7 0101011. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 110 (0x6)
funct7: 0101011 (0x2b)
Instruction Behavior
sha512sig1l is the SHA-512 σ1 low-half instruction (RV32 only). Concatenates rs1 (upper 32 bits) and rs2 (lower 32 bits) as 64-bit input, computes σ1(x) = ROTR(x, 19) ^ ROTR(x, 61) ^ SHR(x, 6), returns bits[31:0] to rd. Paired with sha512sig1h.
Quick Understanding & Search Notes
SHA512SIG1L is a Zknh scalar cryptography instruction for SHA-512 RV32 split transform. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
sha512sig1l computes one half of a SHA-512 64-bit sigma result on RV32 and must be paired with the matching h/l instruction.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
RV32 SHA-512 split forms need the official h/l or reversed-source sequence to assemble the full 64-bit result.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «sha512sig1l a0, a1, a2».
Hash Algorithms
Understand this scenario with real code like «sha512sig1l a0, a1, a2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
RV32 only. rs1=upper 32 bits, rs2=lower 32 bits.
Must be paired with sha512sig1h.
FAQ
Is SHA512SIG1L a complete algorithm implementation?
No. It is a low-level step from AES, SHA, SM3, or SM4; software still combines instructions with the algorithm schedule, round constants, or round keys.