Does SHA512SIG1 use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SHA512SIG1
RISC-V SHA512SIG1 Instruction Details
Instruction ManualI-typeSHA-512 σ1 function (RV64): ROTR(rs1,19) ^ ROTR(rs1,61) ^ SHR(rs1,6)
Instruction Syntax
sha512sig1 rd, rs1
Operand Breakdown
rd: receives the 64-bit SHA-512 Sigma1 result; a write to rd=x0 is discarded.
rs1: supplies the complete 64-bit X(rs1) input; this instruction is defined only for RV64.
Bits 31..20 are fixed to 000100000111. They are an encoding selector, not an assembly immediate and not a 12-bit signed value to sign-extend.
ZknhCrypto & Security
Instruction Behavior
sha512sig1 implements SHA-512 σ1 (RV64 only): σ1(x) = ROTR(x, 19) ^ ROTR(x, 61) ^ SHR(x, 6). Reads 64-bit rs1, computes σ1, writes to rd. For SHA-512 message schedule. On RV32, sha512sig1h/sha512sig1l provide the split implementation.
SHA512SIG1 Decode And Execute Animation
Bounded teaching inputs execute the official SHA-512 fixed-width bit operations; this does not model a complete algorithm or microarchitecture.
rd
rs1
sha512sig1
,
SHA512SIG1 is defined only for RV64 and operates on the complete 64-bit X(rs1).
fixed selector
source
fixed
destination
OP-IMM
31..20
000100000111
19..15
rs1=x11
14..12
001
11..7
rd=x10
6..0
0010011
Execution Data Path
inb
0x0123456789ABCDEF
ror64(inb, 19)
0x79BDE02468ACF135
ror64(inb, 61)
0x091A2B3C4D5E6F78
inb >> 6
0x00048D159E26AF37
result
0x70A3460DBBD4317A
Architectural Result
a0(x10) = 0x70A3460DBBD4317A
This animation shows only official ISA fields and architectural state; it does not model a complete hash algorithm, pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
SHA512SIG1 is a Zknh scalar cryptography instruction for SHA-512 RV64 transform. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
sha512sig1 is the RV64 SHA-512 lowercase sigma message-schedule transform.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «sha512sig1 a0, a1».
Hash Algorithms
Understand this scenario with real code like «sha512sig1 a0, a1».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
RV64 only. On RV32 use sha512sig1h + sha512sig1l.
Rotate/shift amounts (19, 61, 6) differ from SHA-256 σ1 (17, 19, 10).
FAQ
Is SHA512SIG1 a complete algorithm implementation?
No. It implements one SHA-512 Sigma1 transform; software still schedules the remaining SHA-512 computation.