Does SHA512SIG1 use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SHA512SIG1
RISC-V SHA512SIG1 Instruction Details
Instruction ManualI-typeSHA-512 σ1 function (RV64): ROTR(rs1,19) ^ ROTR(rs1,61) ^ SHR(rs1,6)
Instruction Syntax
sha512sig1 rd, rs1
Syntax is sha512sig1 rd, rs1; operands select integer x0–x31 or ABI names, with no assembly immediate.
32-bit OP-IMM: bits31..20=000100000111, funct3=001, opcode=0010011; the fixed selector is not a second operand.
RV64 Zknh only (also included in Zkn/Zk); σ1 XORs 64-bit right rotations by 19 and 61 with the logical right shift by 6.
An x0 source is zero and writes to x0 are discarded; overlapping operands read values before writeback. Equal sources share one value. Execution latency must be data-independent.
ZknhCrypto & Security
Instruction Behavior
sha512sig1 is an RV64 Zknh instruction: σ1(x) = ror64(x,19) ^ ror64(x,61) ^ (x >> 6). The input x is the complete 64-bit X(rs1); rd receives the 64-bit result. Rotations stay within 64 bits and >> zero-fills. RV32 uses a sha512sig1l/sha512sig1h sequence for the full transform.
SHA512SIG1 Decode And Execute Animation
Bounded teaching inputs execute the official SHA-512 fixed-width bit operations; this does not model a complete algorithm or microarchitecture.
rd
rs1
sha512sig1
,
Initially rd shares the source value when rd=rs1; otherwise the demo starts rd at 0. An rs1=x0 source always reads 0. SHA512SIG1 is defined only for RV64 and operates on the complete 64-bit X(rs1).
fixed selector
source
fixed
destination
OP-IMM
31..20
000100000111
19..15
rs1=x11
14..12
001
11..7
rd=x10
6..0
0010011
Execution Data Path
inb
0x0123456789ABCDEF
ror64(inb, 19)
0x79BDE02468ACF135
ror64(inb, 61)
0x091A2B3C4D5E6F78
inb >> 6
0x00048D159E26AF37
result
0x70A3460DBBD4317A
Architectural Result
a0(x10) = 0x0000000000000000
This animation shows only official ISA fields and architectural state; it does not model a complete hash algorithm, pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
SHA-512 σ1 function (RV64): ROTR(rs1,19) ^ ROTR(rs1,61) ^ SHR(rs1,6)
sha512sig1 uses integer X registers with XLEN=64.
Execution latency must not depend on the data being processed; no particular cycle count is specified.
A write to x0 is discarded; source values are read before this instruction writes back.
Common Usage Scenarios
SHA-512 hash transforms
RV64 Zknh, a1=1: the 64-bit rotations yield 0x0000200000000000 and 0x0000000000000008; the logical-shift term is 0, so a0=0x0000200000000008.
Integer-register bit operations
RV64 Zknh, a1=1: the 64-bit rotations yield 0x0000200000000000 and 0x0000000000000008; the logical-shift term is 0, so a0=0x0000200000000008.
Pre-Use Checklist
Syntax Check
- Syntax is sha512sig1 rd, rs1; operands select integer x0–x31 or ABI names, with no assembly immediate.
- 32-bit OP-IMM: bits31..20=000100000111, funct3=001, opcode=0010011; the fixed selector is not a second operand.
Semantic Check
- RV64 Zknh only (also included in Zkn/Zk); σ1 XORs 64-bit right rotations by 19 and 61 with the logical right shift by 6.
- An x0 source is zero and writes to x0 are discarded; overlapping operands read values before writeback. Equal sources share one value. Execution latency must be data-independent.
Pitfalls / Common Confusions
Defined only on RV64; RV32 uses the sha512sig1l/sha512sig1h split forms.
Rotations are 64-bit rotations; the shift by 6 zero-fills and is not an arithmetic shift.
FAQ
Is SHA512SIG1 a complete algorithm implementation?
It computes one 64-bit SHA-512 σ1 transform, not the complete SHA-512 algorithm.