Can SW.AQRL use offset(rs1)?
No. The official syntax is sw.aqrl rs2, (rs1), with no offset immediate; the address comes directly from rs1.
SW.AQRL
RISC-V SW.AQRL Instruction Details
Instruction ManualR-typeZalasr atomic store of 4 bytes with acquire+release-RCsc ordering.
Instruction Syntax
sw.aqrl rs2, (rs1)
Operand Breakdown
Source rs2: supplies the low bits written to memory; the B/H/W/D form selects the width.
Address register rs1: directly supplies the memory address; Zalasr syntax has no offset immediate.
Encoding field rd is fixed to 00000/x0; rl must be 1, and aq/rl only annotate ordering.
ZalasrCache & Synchronization
Instruction Behavior
SW.AQRL is a 4-byte ordered atomic store in the Zalasr standalone load-acquire/store-release family. It atomically writes the low 32 bits of x[rs2] to the address in x[rs1]; the syntax has no offset field, and rd is fixed to x0 in the encoding. The address is naturally aligned to the access width by default unless relaxed by the misaligned atomicity granule PMA.
SW.AQRL Zalasr Decode And Execute Animation
Shows the Zalasr standalone store-release AMO encoding, no-offset address syntax, 32-bit data transfer, and aq/rl ordering annotation.
rs2
rs1
sw.aqrl,()
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00111
funct5
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aq
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rl
01011
rs2
01010
rs1
010
funct3
00000
rd=00000
0101111
opcode
Zalasr Data Path
instruction
0x3EB5202F
opcode
0101111 -> AMO major opcode
funct5
00111 -> SW.AQRL
aq / rl
1/1 -> acquire+release
operands
rs2=a1(x11), rs1=a0(x10), rd=x0
address
a0(x10) -> 0x00001000 (no offset)
store source
low 32 bits of a1(x11) -> 0x89ABCDEF
execute
atomic store 32 bits at 0x00001000
writeback
mem[0x00001000] = 0x89ABCDEF
32-bit Transfer View
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rs2 low 32
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SW.AQRL writes only the low 32 bits of rs2 to memory; higher rs2 bits are not part of the stored value.
This animation shows ISA-visible Zalasr atomic load/store behavior and aq/rl ordering annotations; it does not model LR/SC reservations, AMO read-modify-write old-value return, caches, buses, or pipeline timing.
Quick Understanding & Search Notes
SW.AQRL uses rs1 directly as the address and atomically writes the low 32 bits of rs2; aq/rl bits provide ordering annotations and do not change the stored data.
The syntax is sw.aqrl rs2, (rs1), with no offset field; the address comes from x[rs1].
funct5=00111 selects the Zalasr store-release class, funct3=010 selects the SW.AQRL access width, the AMO major opcode is 0101111, the rl bit must be 1 for Zalasr stores, and rd is fixed to x0.
The stored value comes from the low 32 bits of x[rs2].
aq/rl describe memory ordering only; they do not change the stored data and do not return the old memory value.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «sw.aqrl x5, (x6)».
Concurrency & Multi-core
Understand this scenario with real code like «sw.aqrl x5, (x6)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The syntax has no offset immediate; the address comes directly from rs1.
The store uses only the low 32 bits of rs2; higher bits are not part of the written value.
Zalasr store encodings without rl set are RESERVED.
Zalasr is a single ordered atomic load/store instruction, not an LR/SC reservation protocol or an AMO read-modify-write old-value return.
FAQ
Is SW.AQRL an LR/SC or AMO read-modify-write operation?
No. These Zalasr instructions are single ordered atomic load/store operations; the animation does not show reservations or old-value return.
Do aq/rl bits change the data result?
No. aq/rl are ordering annotations; the stored value is still the low 32 bits of rs2.