How does VANDN.VX use masking?
Append optional v0.t for vm=0; omit it for vm=1. vm is an encoding field, not an assembly register operand. Mask and register-group overlap constraints still apply.
VANDN.VX
RISC-V VANDN.VX Instruction Details
Instruction ManualV-typeVector-scalar bitwise AND-NOT: vd[i] = vs2[i] & ~x[rs1].
Instruction Syntax
vandn.vx vd, vs2, rs1[, v0.t]
vd, vs2 select v0–v31; rs1 selects x0–x31, with x0 always zero. Optional v0.t means vm=0; omission means vm=1. No immediate operand.
32-bit OP-V: funct6=000001, vm[25], vs2[24:20], rs1[19:15], funct3=100, vd[11:7], opcode=1010111.
Zvbb or Zvkb: Zve32x supports SEW=8/16/32, with 64 added by Zve64x. Sign-extend or truncate x[rs1] to SEW, then compute vs2[i]&~x[rs1].
Enable vector state and use a legal supported vtype. Same-width sources/destination may overlap, reading original source values; LMUL>1 groups must be aligned. A masked destination cannot overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
Process mask-enabled elements where vstart≤i<vl. Prestart elements are undisturbed; inactive/tail elements follow vma/vta and may retain values or become all ones. vstart≥vl (including vl=0) changes no destination. Success resets vstart; implementations may reject unsupported nonzero vstart.
ZvbbZvkbVector Bit Manipulation
Instruction Behavior
vandn.vx sign-extends or truncates x[rs1] to SEW, inverts it, then ANDs it with vs2[i]: vd[i] = vs2[i] & ~x[rs1].
VANDN.VX Decode & Execute Animation
This bounded model shows only lane 0 ISA-visible state; it does not model a pipeline, a cryptographic protocol, or unspecified inactive/tail values.
Execution context: enable the listed extension and vector state, use a legal supported vtype, LMUL=1 and VLEN≥64×SEW. Only lane 0 is expanded; vl=32/64 does not replicate it to other elements. SEW=64 requires Zve64x. Nonzero vstart assumes implementation support; otherwise an illegal-instruction exception is permitted.
Bounded execution context
32-bit OP-V encoding fields
31..26
funct6
000001
25
vm
1
24..20
vs2
01000
19..15
rs1
01011
14..12
funct3
100
11..7
vd
00100
6..0
OP-V
1010111
Execution data path
funct6=000001, funct3=100, Zvbb/Zvkb
v4[0] <- pending
Quick Understanding & Search Notes
vandn.vx is provided by Zvbb/Zvkb for vector-scalar and-not. The current supported vtype.SEW selects element width.
vandn.vx sign-extends or truncates x[rs1] to SEW, inverts it, then ANDs it with vs2[i]: vd[i] = vs2[i] & ~x[rs1].
Process active elements where vstart≤i<vl and the mask enables execution. Prestart elements are undisturbed; masked-off and tail elements follow vma/vta, with agnostic values retained or set to all ones. vstart≥vl (including vl=0) leaves all destinations unchanged. Success resets vstart; implementations may reject nonzero vstart.
Same-width source/destination groups may overlap and read original source values; groups must follow LMUL alignment. A masked destination may not overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
Vector Execution Context
vd, vs2 select v0–v31; rs1 selects x0–x31, with x0 always zero. Optional v0.t means vm=0; omission means vm=1. No immediate operand.
32-bit OP-V: funct6=000001, vm[25], vs2[24:20], rs1[19:15], funct3=100, vd[11:7], opcode=1010111.
Zvbb or Zvkb: Zve32x supports SEW=8/16/32, with 64 added by Zve64x. Sign-extend or truncate x[rs1] to SEW, then compute vs2[i]&~x[rs1].
Enable vector state and use a legal supported vtype. Same-width sources/destination may overlap, reading original source values; LMUL>1 groups must be aligned. A masked destination cannot overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
Process mask-enabled elements where vstart≤i<vl. Prestart elements are undisturbed; inactive/tail elements follow vma/vta and may retain values or become all ones. vstart≥vl (including vl=0) changes no destination. Success resets vstart; implementations may reject unsupported nonzero vstart.
Common Usage Scenarios
Apply vector-scalar and-not to active vector elements.
With the listed extension and vector state enabled, legal vtype, LMUL=1, VLEN≥128, vl=1, vstart=0 and no mask: SEW=8, x11=0xCC, v8[0]=0xF0: 0xF0 & ~0xCC = 0x30, written to v4[0].
Pre-Use Checklist
Syntax Check
- vd, vs2 select v0–v31; rs1 selects x0–x31, with x0 always zero. Optional v0.t means vm=0; omission means vm=1. No immediate operand.
- 32-bit OP-V: funct6=000001, vm[25], vs2[24:20], rs1[19:15], funct3=100, vd[11:7], opcode=1010111.
Semantic Check
- Zvbb or Zvkb: Zve32x supports SEW=8/16/32, with 64 added by Zve64x. Sign-extend or truncate x[rs1] to SEW, then compute vs2[i]&~x[rs1].
- Enable vector state and use a legal supported vtype. Same-width sources/destination may overlap, reading original source values; LMUL>1 groups must be aligned. A masked destination cannot overlap v0; v0 cannot supply both SEW data and an EEW=1 mask.
- Process mask-enabled elements where vstart≤i<vl. Prestart elements are undisturbed; inactive/tail elements follow vma/vta and may retain values or become all ones. vstart≥vl (including vl=0) changes no destination. Success resets vstart; implementations may reject unsupported nonzero vstart.
Pitfalls / Common Confusions
rs1 is broadcast at SEW width and inverted; vs2 is not inverted.
The result is vd[i] = vs2[i] & ~x[rs1].
FAQ
Which element widths does VANDN.VX support?
Zve32x implementations provide 8, 16 and 32 bits; Zve64x also provides 64 bits. Use a vtype setting supported by the implementation.