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VANDN.VX

RISC-V VANDN.VX Instruction Details

Instruction ManualV-type

Vector-scalar bitwise AND-NOT: vd[i] = vs2[i] & ~x[rs1].

Instruction Syntax

vandn.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
ZvbbVector Bit Manipulation
Related Search Terms
vandn.vx instructionRISC-V vandn.vxvandn.vx syntaxvandn.vx encodingZvbbvector-scalar bitwise and-not

Instruction Behavior

vandn.vx sign-extends or truncates x[rs1] to SEW, inverts it, then ANDs it with vs2[i]: vd[i] = vs2[i] & ~x[rs1].

VANDN.VX Decode & Execute Animation

This bounded model shows only lane 0 ISA-visible state; it does not model a pipeline, a cryptographic protocol, or unspecified inactive/tail values.

Bounded execution context
32-bit OP-V encoding fields
31..26
funct6
000001
25
vm
1
24..20
vs2
01000
19..15
rs1
01011
14..12
funct3
100
11..7
vd
00100
6..0
OP-V
1010111
Execution data path

funct6=000001, funct3=100, Zvbb

v4[0] <- pending

Quick Understanding & Search Notes

VANDN.VX is a Zvbb vector instruction for vector-scalar bitwise and-not. This page is checked against the official vector crypto extension and V-extension execution model.

vd[i] = vs2[i] & ~x[rs1], with the scalar used at SEW width.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
RISC-V Unprivileged ISA Manual: Vector cryptography extensions 1.0RISC-V Unprivileged ISA Manual: V standard vector extension

Vector Execution Context

When reading VANDN.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Vector Acceleration

Understand this scenario with real code like «vandn.vx vd, vs2, a1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is V-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

rs1 is broadcast at SEW width and inverted; vs2 is not inverted.
The result is vd[i] = vs2[i] & ~x[rs1].

FAQ

Can VANDN.VX always use a v0.t mask?

It can use the vm mask operand shown in the syntax; omitting it gives the unmasked form.

What determines the element width for VANDN.VX?

The current vtype SEW determines it, subject to any instruction-specific SEW restrictions in the extension.