Can VANDN.VX always use a v0.t mask?
It can use the vm mask operand shown in the syntax; omitting it gives the unmasked form.
VANDN.VX
RISC-V VANDN.VX Instruction Details
Instruction ManualR-typeVector-scalar bitwise AND-NOT: vd[i] = vs2[i] & ~x[rs1].
Instruction Syntax
vandn.vx vd, vs2, rs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvbbVector Bit Manipulation
Instruction Behavior
vandn.vx inverts the scalar x[rs1] value after sign-extension/truncation to SEW and ANDs it with vs2[i]: vd[i] = vs2[i] & ~x[rs1].
Quick Understanding & Search Notes
VANDN.VX is a Zvbb vector instruction for vector-scalar bitwise and-not. This page is checked against the official vector crypto extension and V-extension execution model.
vd[i] = vs2[i] & ~x[rs1], with the scalar used at SEW width.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vandn.vx vd, vs2, a1».
Vector Acceleration
Understand this scenario with real code like «vandn.vx vd, vs2, a1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
rs1 is broadcast at SEW width and inverted; vs2 is not inverted.
The result is vd[i] = vs2[i] & ~x[rs1].
FAQ
What determines the element width for VANDN.VX?
The current vtype SEW determines it, subject to any instruction-specific SEW restrictions in the extension.