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VANDN.VV

RISC-V VANDN.VV Instruction Details

Instruction ManualR-type

Vector bitwise AND-NOT: vd[i] = vs2[i] & ~vs1[i].

Instruction Syntax

vandn.vv vd, vs2, vs1, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

ZvbbVector Bit Manipulation

Related Search Terms

vandn.vv instruction RISC-V vandn.vv vandn.vv syntax vandn.vv encoding Zvbb vector bitwise and-not

Instruction Behavior

vandn.vv inverts each bit of vs1[i] and ANDs it with the corresponding bits of vs2[i]: vd[i] = vs2[i] & ~vs1[i].

Quick Understanding & Search Notes

VANDN.VV is a Zvbb vector instruction for vector bitwise and-not. This page is checked against the official vector crypto extension and V-extension execution model.

vd[i] = vs2[i] & ~vs1[i]; note that vs1 is the inverted second source in the syntax.

It follows V-extension vl, vstart, vtype, and optional vm mask rules.

RISC-V Unprivileged ISA Manual: Vector cryptography extensions 1.0 RISC-V Unprivileged ISA Manual: V standard vector extension

Vector Execution Context

When reading VANDN.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vandn.vv vd, vs2, vs1».

Vector Acceleration

Understand this scenario with real code like «vandn.vv vd, vs2, vs1».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Note operand order: syntax is vd, vs2, vs1; the second source operand vs1 is inverted, while vs2 is not.

All SEW supported; subject to vstart and restart semantics.

FAQ

Can VANDN.VV always use a v0.t mask?

It can use the vm mask operand shown in the syntax; omitting it gives the unmasked form.

What determines the element width for VANDN.VV?

The current vtype SEW determines it, subject to any instruction-specific SEW restrictions in the extension.