Can VANDN.VV always use a v0.t mask?
An optional v0.t selects vm=0; omitting it selects vm=1. The masked destination register group must not overlap v0.
VANDN.VV
RISC-V VANDN.VV Instruction Details
Instruction ManualOP-V vector-vector formVector bitwise AND-NOT: vd[i] = vs2[i] & ~vs1[i].
Instruction Syntax
vandn.vv vd, vs2, vs1[, v0.t]
vd, vs2 and vs1 select vector registers v0–v31. Optional v0.t selects vm=0; omitting it selects vm=1. There is no immediate.
32-bit OP-V: funct6=000001, vm[25], vs2[24:20], vs1[19:15], funct3=000, vd[11:7], opcode=1010111.
Available in Zvbb or Zvkb. For active elements, compute vd[i]=vs2[i]&~vs1[i] within current SEW. Zve32x provides SEW 8/16/32; Zve64x adds 64. There is no AES element-group constraint.
Process vstart≤i<vl; masked-off elements follow vma, tails follow vta and prestart elements are undisturbed. A masked destination group must not overlap v0, which also cannot supply SEW-wide data and an EEW=1 mask simultaneously. Equal-width sources/destination may overlap and read original source values. vstart≥vl (including vl=0) updates no destination; ordinary agnostic elements may retain their value or become all ones, rather than necessarily zero.
ZvbbZvkbVector Bit Manipulation
Instruction Encoding
31..26
funct6=000001
25
vm
24..20
vs2
19..15
vs1
14..12
000
11..7
vd
6..0
1010111
VANDN.VV uses opcode 1010111 (0x57), funct3 000. 32-bit OP-V: funct6=000001, vm[25], vs2[24:20], vs1[19:15], funct3=000, vd[11:7], opcode=1010111.
Format: OP-V OPIVV (funct6=000001, vm, vs2, vs1)
opcode: 1010111 (0x57)
funct3: 000 (0x0)
Instruction Behavior
For each active element, vandn.vv computes vd[i] = vs2[i] & ~vs1[i] within the current SEW. It is available in Zvbb or its subset Zvkb. Omitting v0.t selects unmasked execution; with v0.t, only active elements with v0.mask[i]=1 execute.
Quick Understanding & Search Notes
Vector bitwise AND-NOT: vd[i] = vs2[i] & ~vs1[i].
vd[i] = vs2[i] & ~vs1[i]; note that vs1 is the inverted second source in the syntax.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
Vector Execution Context
vd, vs2 and vs1 select vector registers v0–v31. Optional v0.t selects vm=0; omitting it selects vm=1. There is no immediate.
32-bit OP-V: funct6=000001, vm[25], vs2[24:20], vs1[19:15], funct3=000, vd[11:7], opcode=1010111.
Available in Zvbb or Zvkb. For active elements, compute vd[i]=vs2[i]&~vs1[i] within current SEW. Zve32x provides SEW 8/16/32; Zve64x adds 64. There is no AES element-group constraint.
Process vstart≤i<vl; masked-off elements follow vma, tails follow vta and prestart elements are undisturbed. A masked destination group must not overlap v0, which also cannot supply SEW-wide data and an EEW=1 mask simultaneously. Equal-width sources/destination may overlap and read original source values. vstart≥vl (including vl=0) updates no destination; ordinary agnostic elements may retain their value or become all ones, rather than necessarily zero.
Common Usage Scenarios
Crypto & Security
Zvbb or Zvkb, SEW=8, vl=1, vstart=0, unmasked, vs2[0]=0xF0 and vs1[0]=0xCC: 0xF0 & ~0xCC = 0x30, written to vd[0].
Vector Acceleration
Zvbb or Zvkb, SEW=8, vl=1, vstart=0, unmasked, vs2[0]=0xF0 and vs1[0]=0xCC: 0xF0 & ~0xCC = 0x30, written to vd[0].
Pre-Use Checklist
Syntax Check
- vd, vs2 and vs1 select vector registers v0–v31. Optional v0.t selects vm=0; omitting it selects vm=1. There is no immediate.
- 32-bit OP-V: funct6=000001, vm[25], vs2[24:20], vs1[19:15], funct3=000, vd[11:7], opcode=1010111.
Semantic Check
- Available in Zvbb or Zvkb. For active elements, compute vd[i]=vs2[i]&~vs1[i] within current SEW. Zve32x provides SEW 8/16/32; Zve64x adds 64. There is no AES element-group constraint.
- Process vstart≤i<vl; masked-off elements follow vma, tails follow vta and prestart elements are undisturbed. A masked destination group must not overlap v0, which also cannot supply SEW-wide data and an EEW=1 mask simultaneously. Equal-width sources/destination may overlap and read original source values. vstart≥vl (including vl=0) updates no destination; ordinary agnostic elements may retain their value or become all ones, rather than necessarily zero.
Pitfalls / Common Confusions
vs1 is the inverted second source in assembly syntax; vs2 is not inverted.
Use implementation-supported SEW: Zve32x provides 8/16/32 and Zve64x additionally provides 64, not arbitrary widths.
A masked destination group must not overlap v0; such encodings are reserved. Inactive and tail elements follow vma/vta, rather than universally becoming zero or remaining unchanged.
FAQ
What determines the element width for VANDN.VV?
vtype.SEW and implementation support determine it: Zve32x provides 8/16/32 and Zve64x adds 64. This instruction has neither the AES SEW=32 constraint nor its 128-bit element-group restriction.