Is the VAND.VI immediate zero-extended?
No. RVV integer immediate logical forms use a 5-bit signed immediate sign-extended to SEW.
VAND.VV
RISC-V VAND.VV Instruction Details
Instruction ManualR-typeBitwise AND each vs2 element with vs1: vd[i]=vs2[i] & vs1.
Instruction Syntax
vand.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector OperationsBitwise Operations
Instruction Behavior
VAND.VV performs bitwise AND for each active element. Both vector source elements participate at the current SEW width.
Quick Understanding & Search Notes
VAND.VV is RVV integer bitwise AND, useful for keeping selected bits in each element.
The result is a bitwise logical value, not a comparison mask.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Common Usage Scenarios
Bit Masks
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vand.vv v1, v2, v3».
Logic Ops
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vand.vv v1, v2, v3».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vand.vi: immediate sign-extended — negative produces upper 1s. vand.vx: scalar truncated. vand.vv: same EEW.