Is VOR.VV a mask logical instruction?
No. It writes ordinary vector elements; mask-register logic uses dedicated instructions such as VMOR.MM.
VOR.VV
RISC-V VOR.VV Instruction Details
Instruction ManualR-typeElement-wise bitwise OR.
Instruction Syntax
vor.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector IntegerBitwise
Related Search Terms
Instruction Behavior
VOR.VV performs bitwise OR on active elements, ORing vs2 with the corresponding vs1 element and writing vd.
Quick Understanding & Search Notes
VOR.VV is ordinary vector integer logical OR, useful for setting bit fields or combining data bit patterns outside mask-register logic.
Only active elements are written; inactive and tail elements follow vma/vta policies.
The VI immediate is a 5-bit signed immediate extended to SEW.
Do not confuse this with VMOR.MM, which operates on mask-register bits.
Common Usage Scenarios
Flag Setting
Understand this scenario with real code like «vor.vv v8, v12, v4, v0.t».
Mask Merging
Understand this scenario with real code like «vor.vv v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Same function as vor.vi/vor.vx but both operands from vector registers