How is the VOR.VX scalar converted to SEW?
XLEN>SEW takes low SEW bits; XLEN<SEW sign-extends. x0 supplies zero, so active results equal vs2.
VOR.VX
RISC-V VOR.VX Instruction Details
Instruction ManualOPIVX (OP-V)VOR.VX applies SEW-width integer bitwise OR to active RVV elements.
Instruction Syntax
vor.vx vd, vs2, rs1[, v0.t]
Operand Breakdown
Syntax: vor.vx vd, vs2, rs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=100 (OPIVX), funct6=001010.
vd/vs2 are SEW/LMUL vector groups; rs1 supplies an integer scalar. XLEN>SEW takes low SEW bits; XLEN<SEW sign-extends; x0 supplies zero. Active results are vs2[i] | scalar.
Active body satisfies vstart≤i<vl with mask enabled. Prestart is unchanged; inactive/tail follow vma/vta, with agnostic retaining old values or writing all ones. vstart≥vl (including vl=0) updates no destination elements.
Same-width source/destination overlap is legal. Group starts align to EMUL, EMUL≤8. Masked vd excludes v0; v0 cannot supply both the EEW=1 mask and SEW source data.
Require V 1.0, enabled vector state and valid supported vtype/SEW. Successful execution resets vstart to 0. The animation uses its stated m1/vstart=0 assumptions; its steps are not processor cycles.
VVector IntegerBitwise
Instruction Behavior
VOR.VX computes vd[i]=vs2[i] | scalar for active elements. x[rs1] supplies the scalar: XLEN>SEW uses low SEW bits; XLEN<SEW sign-extends; x0 supplies zero. Omitting v0.t is unmasked; including it selects body elements with v0.mask[i]=1.
VOR.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VOR applies SEW-width bitwise OR to active elements and writes vd.
Instruction input
vor.vx
Require V 1.0, enabled vector state and valid supported vtype/SEW. Fix LMUL=m1, vstart=0, VLEN=4096 and VLMAX=4096/16=256. An ordinary masked vd cannot be v0; equal-width source/destination overlap is legal. XLEN>SEW takes low scalar bits; XLEN<SEW sign-extends; x0 supplies zero. When v0 supplies the EEW=1 mask it cannot also supply SEW data. VL=0 updates no destination elements. Only body is shown without definite inactive/tail values. Steps are teaching stages, not processor cycles.
Execution Context
OP-V encodingvor.vx
funct6
001010
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
|
|
|
|
|
|
|
|
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vor.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows OP-V field decode, active-element reads, SEW-width integer bitwise OR, mask control, and vd writeback. These are teaching stages; they do not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VOR.VX is a V-extension single-width integer logical instruction: within vl, active elements compute vs2 | the second source, keep the SEW-bit result, and write ordinary vector register vd.
32-bit OP-V: opcode=1010111, funct6=001010, funct3=100; rs1 is an integer register.
XLEN>SEW takes low SEW bits; XLEN<SEW sign-extends. Active results are vs2[i] | scalar.
Active body: vstart≤i<vl and (vm=1 or v0.mask[i]=1). Prestart unchanged; inactive/tail follow vma/vta: retain or all ones for agnostic.
Same-width overlap is legal. Group starts align to EMUL, EMUL≤8. Masked vd excludes v0; v0 cannot supply both the EEW=1 mask and SEW data.
Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart≥vl, including vl=0, updates no destination elements.
Vector Execution Context
Syntax: vor.vx vd, vs2, rs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=100 (OPIVX), funct6=001010.
vd/vs2 are SEW/LMUL vector groups; rs1 supplies an integer scalar. XLEN>SEW takes low SEW bits; XLEN<SEW sign-extends; x0 supplies zero. Active results are vs2[i] | scalar.
Active body satisfies vstart≤i<vl with mask enabled. Prestart is unchanged; inactive/tail follow vma/vta, with agnostic retaining old values or writing all ones. vstart≥vl (including vl=0) updates no destination elements.
Same-width source/destination overlap is legal. Group starts align to EMUL, EMUL≤8. Masked vd excludes v0; v0 cannot supply both the EEW=1 mask and SEW source data.
Require V 1.0, enabled vector state and valid supported vtype/SEW. Successful execution resets vstart to 0. The animation uses its stated m1/vstart=0 assumptions; its steps are not processor cycles.
Common Usage Scenarios
setting selected bits, combining bit fields, or merging per-element data bit patterns
Assume enabled V/VS, valid m1, VLEN≥128, supported SEW, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=16, x11=0x8000, v8=[1,2,3,4] → v4=[32769,32770,32771,32772]. Element-wise OR uses low 16 scalar bits for XLEN=32/64. vl=0 leaves the destination unchanged.
RVV per-element bit operations
Assume enabled V/VS, valid m1, VLEN≥128, supported SEW, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=16, x11=0x8000, v8=[1,2,3,4] → v4=[32769,32770,32771,32772]. Element-wise OR uses low 16 scalar bits for XLEN=32/64. vl=0 leaves the destination unchanged.
Pre-Use Checklist
Syntax Check
- Syntax: vor.vx vd, vs2, rs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=100 (OPIVX), funct6=001010.
- vd/vs2 are SEW/LMUL vector groups; rs1 supplies an integer scalar. XLEN>SEW takes low SEW bits; XLEN<SEW sign-extends; x0 supplies zero. Active results are vs2[i] | scalar.
Semantic Check
- Active body satisfies vstart≤i<vl with mask enabled. Prestart is unchanged; inactive/tail follow vma/vta, with agnostic retaining old values or writing all ones. vstart≥vl (including vl=0) updates no destination elements.
- Same-width source/destination overlap is legal. Group starts align to EMUL, EMUL≤8. Masked vd excludes v0; v0 cannot supply both the EEW=1 mask and SEW source data.
- Require V 1.0, enabled vector state and valid supported vtype/SEW. Successful execution resets vstart to 0. The animation uses its stated m1/vstart=0 assumptions; its steps are not processor cycles.
Pitfalls / Common Confusions
VOR.VX writes ordinary SEW-width vector elements, not a one-bit-per-element mask.
The related VI form uses a 5-bit signed immediate in -16..15; larger constants normally come from an integer register through the .vx form.
Masked-off and tail elements follow the current vtype vma/vta policies; do not assume fixed zeroing or fixed preservation.
FAQ
Does VOR.VX produce a mask or zero inactive elements?
It writes ordinary SEW elements, not a mask. Inactive follows vma and tail follows vta; agnostic may retain old values or become all ones, without guaranteed zeroing.